Sense amplifier and method for sensing signals in a silicon-on-insulator integrated circuit

• US 6,433,589 B1
• Filed: 04/12/2001
• Issued: 08/13/2002
• Est. Priority Date: 04/12/2001
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lee, Michael Ju Hyeok
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TRAN, ANH Q
• Application Number:
  US09/833,428
• Time in Patent Office: 488 Days
• Field of Search: 326/95, 326/98, 326/112, 326/115, 326/119, 326/121
• US Class Current: 326/115
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356139 with synchronous operation

Abstract

An improved sense amplifier ad method for sensing signals in a silicon-on-insulator (SOI) integrated circuit improve the performance of semiconductor memories and other circuits implemented in SOI technology. The bodies of amplifier transistors within the sense amplifier and bodies of input transistors to the sense amplifier are coupled to corresponding input signals, eliminating the history dependance that would result from unconnected bodies, while achieving faster switching times due to a dynamically produced difference in threshold voltage of the input transistors and amplifier transistors. The switching time is improved over circuits using input transistors and amplifier transistors having statically biased bodies.

Claims

1. A dynamic logic circuit fabricated on a substrate, said dynamic logic circuit comprising:

a sense amplifier including a first latch transistor having a body insulated from said substrate, and a second latch transistor having a first channel connection coupled to a gate of said first latch transistor and a gate coupled to a second channel connection of said first latch transistor, whereby said first latch transistor and second latch transistor form a cross-coupled pair; and

a first input transistor, having a body insulated from said substrate, connected in functional series with said first latch transistor, wherein a voltage of said body of said first latch transistor and a voltage of said body of said first input transistor are adjusted in conformity with an input of said dynamic logic circuit to improve switching of said sense amplifier, and wherein said input of said dynamic logic circuit is coupled to a gate of said first input transistor, and wherein a first channel connection of said first input transistor is coupled to a first channel connection of said first latch transistor.

2. The dynamic logic circuit of claim 1, wherein said first input transistor is coupled to said first latch transistor, and wherein a body of said first latch transistor and said body of said first input transistor are coupled to said input of said dynamic logic circuit, wherein a threshold voltage of said first latch transistor and a threshold voltage of said second latch transistor are adjusted in conformity with said input of said dynamic logic circuit, whereby improved switching of said sense amplifier is achieved.

3. The dynamic logic circuit of claim 1, further comprising a second input transistor having a gate coupled to a complementary input of said dynamic logic circuit, an isolated body coupled to said complementary input, and a first channel connection coupled to a second channel connection of said second latch transistor.

4. The dynamic logic circuit of claim 3, wherein said sense amplifier further comprises:

a third latch transistor of complementary type to said first latch transistor and having a gate coupled to said gate of said first latch transistor and a channel connection coupled to said second channel connection of said first latch transistor; and

a fourth latch transistor of complementary type to said second latch transistor and having a gate coupled to said gate of said second latch transistor and a channel connection coupled to said first channel connection of said second latch transistor, whereby said first latch transistor, said second latch transistor, said third latch transistor and said fourth latch transistor form a complementary cross-coupled amplifier.

5. The dynamic logic circuit of claim 4, further comprising a pre-charge circuit coupled to a sense enable input of said dynamic logic circuit and further coupled to said second channel connection of said first latch transistor and said first channel connection of said second latch transistor, for pre-setting the state of said complementary cross-coupled amplifier when said sense enable input is inactive.

6. The dynamic logic circuit of claim 5, further comprising a foot transistor having a first channel connection coupled to a second channel connection of said first input transistor and further coupled to a second channel connection of said second input transistor, wherein said foot transistor has a gate coupled to said sense enable input and a second channel connection coupled to a power supply rail for permitting conduction of said first input transistor and said second input transistor only when said sense enable input is active.

7. The dynamic logic circuit of claim 6, wherein said dynamic logic circuit is fabricated in silicon-on-insulator technology.

8. The dynamic logic circuit of claim 1, wherein said dynamic logic circuit is fabricated in silicon-on-insulator technology.

9. A dynamic logic circuit fabricated on a substrate, said dynamic logic circuit comprising:

a first latch transistor having a body insulated from said substrate;

a second latch transistor having a gate coupled to a second channel connection of said first latch transistor, wherein said first latch transistor has a gate coupled to a first channel connection of said second latch transistor;

a third latch transistor of complementary type to said first latch transistor and having a gate coupled to said gate of said first latch transistor and a channel connection coupled to said second channel connection of said first latch transistor; and

a fourth latch transistor of complementary type to said second latch transistor and having a gate coupled to said gate of said second latch transistor and a channel connection coupled to said first channel connection of said second latch transistor;

a first input transistor having a body insulated from said substrate, connected in functional series with said first latch transistor, wherein a voltage of said body of said first latch transistor and a voltage of said body of said first input transistor are adjusted in conformity with an input of said dynamic logic circuit to improve switching of said sense amplifier said first latch transistor, and wherein a body of said first latch transistor and said body of said first input transistor are coupled to an input of said dynamic logic circuit, whereIn a threshold voltage of said first latch transistor and a threshold voltage of said second latch transistor are adjusted in conformity with said input of said dynamic logic circuit to improve switching of said cross-coupled amplifier.

10. The dynamic logic circuit of claim 9, further comprising:

a first pre-charge transistor having a gate coupled to a sense enable input of said dynamic logic circuit and a channel connection coupled to said second channel connection of said first latch transistor;

a second pre-charge transistor having a gate coupled to said sense enable input and a channel connection coupled to said first channel connection of said second latch transistor.

11. The dynamic logic circuit of claim 10, further comprising a shunt transistor having a gate coupled to a sense enable input of said dynamic logic circuit, a first channel connection coupled to said second channel connection of said first latch transistor, and a second channel connection coupled to said first channel connection of said second latch transistor.

12. The dynamic logic circuit of claim 11, further comprising a foot transistor having a first channel connection coupled to a second channel connection of said first input transistor and further coupled to a second channel connection of said second input transistor, wherein said foot transistor has a gate coupled to said sense enable input and a second channel connection coupled to a power supply rail for permitting conduction of said first input transistor and said second input transistor only when said sense enable input is active.

13. The dynamic logic circuit of claim 10, further comprising a foot transistor having a first channel connection coupled to a second channel connection of said first input transistor and further coupled to a second channel connection of said second input transistor, wherein said foot transistor has a gate coupled to said sense enable input and a second channel connection coupled to a power supply rail for permitting conduction of said first input transistor and said second input transistor only when said sense enable input is active.

14. The dynamic logic circuit of claim 9, wherein said dynamic logic circuit is fabricated in silicon-on-insulator technology.