Single cell rail-to-rail input/output operational amplifier

• US 6,433,637 B1
• Filed: 03/23/2001
• Issued: 08/13/2002
• Est. Priority Date: 03/23/2001
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Sauer, Don R.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): NGUYEN, KHANH V
• Application Number:
  US09/815,779
• Time in Patent Office: 508 Days
• Field of Search: 330/253, 330/255, 330/264, 330/263
• US Class Current: 330/255
• CPC Class Codes: H03F 2200/153 Feedback used to stabilise the amplifier
• CPC Class Codes: H03F 2203/45028 the differential amplifier amplifying transistors are folded cascode coupled transistors
• CPC Class Codes: H03F 2203/45296 the AAC comprising one or more discrete capacitive elements, e.g. a transistor coupled as capacitor
• CPC Class Codes: H03F 2203/45644 the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors
• CPC Class Codes: H03F 3/303 using opamps as driving stages
• CPC Class Codes: H03F 3/45219 Folded cascode stages

Abstract

A method and apparatus is directed to a rail-to-rail MOS amplifier that operates with a very low power supply. An input stage amplifier operates over rail-to-rail common-mode voltages. The input stage amplifier includes two differential input stages that steer current to loads in a class AB turnaround stage. The class AB turnaround stage converts the differential signals into a single signal that is driven into an output stage amplifier. The output stage amplifier includes level shifting buffer amplifiers that are arranged to bias a pair of MOS output transistors. Each level shifting buffer amplifier is arranged to bias a MOS transistor in a sub-threshold operating region such that the MOS transistor operates as a resistor. The MOS resistor works in conjunction with a MOS diode to provide an AB bias voltage to a gate of a respective one of the output transistors. The level shifting buffer amplifiers are also arranged such that the gate of each output transistor is selectively switched to a power supply voltage, providing maximum gate drive to the output transistor when the output transistor drives a maximum current to an external load. A single capacitor may be employed to provide compensation between the output of the amplifier and the output of the class AB turnaround stage. The sub-threshold operation of the level shifting buffer amplifiers permits the output stage amplifier to operate on power supplies down to roughly a single transistor threshold voltage.

Claims

1. An apparatus, operating from a high power supply having a high potential and a low power supply having a low potential, that is arranged to provide a rail-to rail output signal at an output node in response to an input signal at an input node, comprising:

a first active load device, that operates as a sub-threshold device, is coupled to the high power supply and a first intermediary node;

a first diode device is coupled between the first intermediary node and a first drive node, wherein the first diode device is arranged to provide a high drive signal at the first drive node when active and the first diode device is inactive when the input signal is at the low potential;

a first MOS transistor, wherein the gate of the first MOS transistor is coupled to a reference voltage, the drain of the first MOS transistor is coupled to the first drive node, and the source of the first MOS transistor is coupled to a first current source, wherein the first MOS transistor is arranged to couple the first drive node to the low potential when the first diode device is inactive;

a second active load device, tat operates as a sub-threshold device, is coupled to the low power supply and a second intermediary node;

a second diode device is coupled between the second intermediary node and a second drive node, wherein the diode device is arranged to provide a low drive signal at the second drive node when active and the second diode device is inactive when the input signal is at the high potential;

a second MOS transistor, wherein the gate of the second MOS transistor is coupled to the reference voltage, the drain of the second MOS transistor is coupled to the second drive node, and the source of the second MOS transistor is coupled to a second current source, wherein the second MOS transistor is arranged to couple the second drive node to the high potential when the second diode device is inactive; and

a class AB output drive circuit is arranged to provide the rail-to-rail output signal in response to the high drive signal and the low drive signal, wherein the class AB output drive circuit is biased for class AB operation.

2. An apparatus as in claim 1, further comprising a reference circuit that arranged to produce the reference voltage at a reference node in response to the high potential and the low potential, wherein the reference voltage is substantially half-way between the high potential and the low potential.

3. An apparatus as in claim 1, the class AB output drive circuit further comprising:

a first MOS output transistor, wherein the gate of the first MOS output transistor is coupled to the first drive node such that the first diode device provides a class AB bias to the first MOS output transistor at the first drive node; and

a second MOS output transistor, wherein the gate of the second MOS output transistor is coupled to the second drive node such that the second diode device provides another class AB bias to the second MOS output transistor at the second drive node.

4. An apparatus as in claim 1, further comprising a compensation circuit is coupled between the output node and the input node.

5. An apparatus as in claim 1, further comprising a

a third active load device, that operates as a sub-threshold device, is coupled to the high power supply and a third intermediary node, wherein the third active load device and the first active load device are arranged as a first current reflection circuit;

a third MOS transistor, wherein the gate of the third MOS transistor is coupled to the input signal, the drain of the third MOS transistor is coupled to the third intermediary node, and the source of the third MOS transistor is coupled to the first current source, such that the first MOS transistor and the third MOS transistor operate as a first differential pair in a first transconductance amplifier circuit;

a fourth active load device, that operates as a sub-threshold device, is coupled to the low power supply and a fourth intermediary node, wherein the fourth active load device and the second active load device are arranged as a second current reflection circuit; and

a fourth MOS transistor, wherein the gate of the fourth MOS transistor is coupled to the input signal, the drain of the fourth MOS transistor is coupled to the fourth intermediary, and a source of the fourth MOS transistor is coupled to the second current source, such that the second MOS transistor and the fourth MOS transistor operate as a second differential pair in a second transconductance amplifier circuit.

6. An apparatus as in claim 5, wherein the first transconductance amplifier circuit provides a first level shifted signal that is coupled to the first drive node, and the second transconductance amplifier circuit provides a second level shifted signal that is coupled to the second drive node such that the first level shifted signal and the second level shifted signal provide class AB biasing to the class AB output drive circuit.

7. An apparatus as in claim 5, wherein the first transconductance amplifier provides a gain from the input signal to the first drive node, and the second transconductance amplifier provides another gain from the input signal to the second drive node.

8. An apparatus as in claim 5, wherein the first active load device has a first associated area, the second active load device has a second associated area, the third active load device has a third associated area, the fourth active load device has a fourth associated area, the first associated area ratios to the third associated area by a first ratio, and the second associated area ratios to the fourth associated area by a second ratio.

9. An apparatus as in claim 8, wherein the first ratio and the second ratio are substantially two-to-one.

10. An apparatus, operating from a high power supply having a high potential and a low power supply having a low potential, that is arranged to provide a rail-to-rail output signal at an output node in response to a differential input signal, comprising:

an input stage amplifier circuit that produces a single-ended signal from the differential input signal; and

an output stage amplifier circuit that produces the rail-to-rail output signal in response to the single-ended input signal, the output stage amplifier circuit comprising;

a first active load device, that operates as a sub-tbreshold device, is coupled to the high power supply and a first intermediary node;

a first diode device is coupled between the first intermediary node and a first drive node, wherein the first diode device is arranged to provide a high drive signal at the first drive node when active aid the first diode device is inactive when the single-ended input signal is at the low potential;

a first MOS transistor, wherein the gate of the first MOS transistor is coupled to the reference circuit, the drain of the first MOS transistor is coupled to the first drive node, and the source of the first MOS transistor is coupled to a first current source, wherein the first MOS transistor is arranged to couple the first drive node to the low potential when the first diode device is inactive;

a second active load device, that operates as a sub-threshold device, is coupled to the low power supply and a second intermediary node;

a second diode device is coupled between the second intermediary node and a second drive node, wherein the diode device is arranged to provide a low drive signal at the second drive node when active and the second diode device is inactive when the single-ended input signal is at the high potential;

a second MOS transistor, wherein the gate of the second MOS transistor is coupled to the reference circuit, the drain of the second MOS transistor is coupled to the second drive node, and the source of the second MOS transistor is coupled to a second current source, wherein the second MOS transistor is arranged to couple the second drive node to the high potential when the second diode device is inactive; and

a class AB output drive circuit is arranged to provide the rail-to-rail output signal in response to the high drive signal and the low drive signal, wherein the class AB output drive circuit is biased for class AB operation.

11. An apparatus as in claim 10, the input stage amplifier circuit further comprising:

a first transconductance amplifier that includes an NMOS differential pair of transistors that are arranged to provide a first current output at a first node and a second current output at a second node, wherein the first and second current outputs are produced in response to the differential input signal and the NMOS differential pair of transistors are arranged to operate as sub-threshold devices;

a second transconductance amplifier that includes a PMOS differential pair of transistors that are arranged to provide a third current output at a third node and fourth current output at a fourth node, wherein the third and fourth current outputs are produced in response to the differential input signal and the PMOS differential pair of transistors are arranged to operate as sub-threshold devices; and

a class AB turnaround stage circuit produces the single-ended signal in response to the first, second, third, and fourth current outputs.

12. An apparatus as in claim 11, the class AB output drive circuit of the output stage amplifier circuit further comprising:

a first MOS output transistor, wherein the gate of the first MOS output transistor is coupled to the first drive node such that the first diode device provides a class AB bias to the first MOS output transistor at the first drive node; and

a second MOS output transistor, wherein the gate of the second MOS output transistor is coupled to the second drive node such that the second diode device provides another class AB bias to the second MOS output transistor at the second drive node.

13. An apparatus as in claim 12, the output stage amplifier circuit further comprising:

a third active load device, that operates as a sub-threshold device, is coupled to the high power supply and a third intermediary node, wherein the third active load device and the first active load device are arranged as a first current reflection circuit;

a third MOS transistor, wherein the gate of the third MOS transistor is coupled to the input signal, the drain of the third MOS transistor is coupled to the third intermediary node, and the source of the third MOS transistor is coupled to the first current source, such that the first MOS transistor and the third MOS transistor operate as a first differential pair in a first transconductance amplifier circuit;

a fourth active load device, that operates as a sub-threshold device, is coupled to the low power supply and a fourth intermediary node, wherein the fourth active load device and the second active load device are arranged as a second current reflection circuit; and

a fourth MOS transistor, wherein the gate of the fourth MOS transistor is coupled to the input signal, the drain of the fourth MOS transistor is coupled to the fourth intermediary, and a source of the fourth MOS transistor is coupled to the second current source, such that the second MOS transistor and the fourth MOS transistor operate as a second differential pair in a second transconductance amplifier circuit.

14. An apparatus as in claim 11, the class AB turnaround stage of the input stage amplifier circuit further comprising:

a first resistance circuit that is coupled between the first node and the high power supply;

a second resistance circuit that is coupled between the second node and the high power supply;

a third resistance circuit that is coupled between the third node and the low power supply;

a fourth resistance circuit that is coupled between the fourth node and the low power supply;

a first and second PMOS transistor, wherein the source of the first PMOS transistor is coupled to the first node, the source of the second PMOS transistor is coupled to the third node, the gate of the first PMOS transistor is coupled to the gate of the second PMOS transistor, and the drain of the second PMOS transistor is coupled to a third current source;

a first and second NMOS transistor, wherein the source of the first NMOS transistor is coupled to the third node, the source of the second NMOS transistor is coupled to the fourth node, the gate of the first NMOS transistor is coupled to the gate of the second NMOS transistor, and the drain of the second NMOS transistor is arranged to provide a current in response to a fourth current source;

a third and fourth PMOS transistor, wherein the source of the third PMOS transistor is coupled to the first node, the source of the fourth PMOS transistor is coupled to the second node, the gate of the third PMOS transistor is coupled to the gate of the fourth PMOS transistor, the drain of the third PMOS transistor is coupled to the drain of the first NMOS transistor; and

a third and fourth NMOS transistor, wherein the source of the third NMOS transistor is coupled to the third node, the source of the fourth NMOS transistor is coupled to the fourth node, the gate of the third NMOS transistor is coupled to the gate of the fourth NMOS transistor, the drain of the third NMOS transistor is coupled to the drain of the first PMOS transistor, and the drain of the fourth PMOS transistor is coupled to the drain of the fourth NMOS transistor at a common node, wherein the single-ended signal corresponds to a potential of the common-node.

15. An apparatus as in claim 14, wherein the gate of the first NMOS transistor is coupled to the gate of the fourth NMOS transistor through a first compensation circuit, and the gate of the first PMOS transistor is coupled to the gate of the fourth PMOS transistor through a second compensation circuit, wherein the first and second compensation circuits enhance stability in the input stage amplifier.

16. An apparatus as in claim 14, wherein a first compensation circuit is coupled between the source and drain of the fourth NMOS transistor and a second compensation circuit is coupled between the source and the drain of the fourth PMOS transistor, wherein the first and second compensation circuits enhance stability in the input stage amplifier.

17. An apparatus, operating from a high power supply having a high potential and a low power supply having a low potential, that is arranged to provide a rail-to-rail output signal at an output node in response to an input signal at an input node, comprising:

a first means for level shifting that produces a first drive signal that corresponds to a first level shifted version of the input signal, the first means for level shifting providing gain between the input signal and the first drive signal, and the first means for level shifting is arranged to couple the first drive signal to the low potential when the potential of the input signal corresponds to the low potential;

a second means for level shifting that produces a second drive signal that corresponds to a second level shifted version of the input signal, the second means for level shifting providing gain between the input signal and the second drive signal, and the second means for level shifting is arranged to couple the second drive signal to the high potential when the potential of the input signal corresponds to the high potential;

a first output drive means is coupled to the output node, wherein the first output drive means is responsive to the first drive signal; and

a second output drive means is coupled to the output node, wherein the second output drive means is responsive to the second drive signal, the first output drive means is arranged to cooperate with the second output drive means such that the first output drive means and the second output drive means provide the rail-to-rail output signal at the output node.

18. An apparatus, as in claim 17, further comprising a means for converting that is arranged to produce a single-ended signal in response to a rail-to-rail differential input signal, wherein the single-ended signal corresponds to the input signal.

19. An apparatus as in claim 18, the means for converting further comprising:

a first means for generating that produces a first and a second current in response to the rail-to-rail differential input signal, wherein the first means for generating operates with common-mode signals that range up to the high potential;

a second means for generating that produces a third and fourth current in response to the differential signal, wherein the second means for generating operates over common-mode signals that range down to the low potential;

a first means for converting is arranged to convert the first current and the second current into a first signal;

a second means for converting is arranged to convert the third current and the fourth current into a second signal; and

a means for combining is arranged to produce the single-ended signal in response to the first signal and the second signal.

20. An apparatus, operating from a high power supply having a high potential and a low power supply having a low potential, that is arranged to provide a rail-to-rail output signal at an output node in response to an input signal at au input node, comprising:

a first MOS transistor, wherein the source of the first MOS transistor is coupled to the high power supply, the drain of the first MOS transistor is coupled to a first node, and the gate of the first MOS transistor is coupled to a third node;

a second MOS transistor, wherein the source of the second transistor is coupled to the first node, and the gate and source of the second MOS transistor are coupled to a second node;

a third MOS transistor, wherein the drain of the third MOS transistor is coupled to the second node, the source of the third MOS transistor is coupled to a first current source, and the gate of the third MOS transistor is arranged to receive a reference voltage;

a fourth MOS transistor, wherein the source of the fourth MOS transistor is coupled to the high power supply, and the gate and drain of the fourth MOS transistor are coupled to the third node;

a fifth MOS transistor, wherein the drain of the fifth MOS transistor is coupled to the third node, the source of the fifth MOS transistor is coupled to the first current source, and the gate of the fifth MOS transistor is arranged to receive the input signal;

a sixth MOS transistor, wherein the source of the first MOS transistor is coupled to the low power supply, the drain of the sixth MOS transistor is coupled to a fourth node, and the gate of the sixth MOS transistor is coupled to a sixth node;

a seventh MOS transistor, wherein the source of the seventh transistor is coupled to the fourth node, the gate and source of the second MOS transistor are coupled to a fifth node;

an eighth MOS transistor, wherein the drain of the eighth MOS transistor is coupled to the f node, the source of the eighth MOS transistor is coupled to a second current source, and the gate of the eighth MOS transistor is arranged to receive the reference voltage;

a ninth MOS transistor, wherein the source of the ninth MOS transistor is coupled to the low power supply, the gate and dram of the ninth MOS transistor are coupled to the sixth node;

a tenth MOS transistor, wherein the drain of the tenth MOS transistor is coupled to the sixth node, the source of the tenth-MOS transistor is coupled to the second current source, and the gate of the tenth MOS transistor is arranged to receive the input signal.

21. An apparatus as in claim 20, wherein the first MOS transistor, the second MOS transistor, the fourth MOS transistor, the eighth MOS transistor and the tenth MOS transistor are PMOS transistors;

and the third MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the ninth MOS transistor are NMOS transistors.