Programmable clock generator

• US 6,433,645 B1
• Filed: 03/26/1998
• Issued: 08/13/2002
• Est. Priority Date: 10/30/1995
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Mann, Eric N., Torode, John Q.
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US09/048,905
• Time in Patent Office: 1,601 Days
• Field of Search: 331/1.A, 331/2, 331/16, 331/17, 331/18, 331/25, 331/74, 331/108.C, 331/108.D, 327/105, 327/107, 327/147-150, 327/156-159, 455/260
• US Class Current: 331/18
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Claims

1. A circuit for generating a clock signal comprising:

a single-poly EPROM for storing configuration information to determine a frequency of oscillation of said clock signal; and

a clock generator receiving said configuration information and generating said clock signal having said frequency of oscillation,

wherein said single-poly EPROM and said clock generator are on a single chip.

2. The circuit according to claim 1, wherein said configuration information comprises frequency based information for determining the frequency at which the clock signal oscillates and general information for controlling one or more non-frequency parameters of the circuit.

3. The circuit according to claim 1, wherein said configuration information comprises frequency based information for determining the frequency at which the clock signal oscillates and general information for controlling two or more non-frequency parameters of the circuit.

4. The circuit according to claim 1, wherein said configuration information controls said frequency of oscillation and an output multiplexer.

5. The circuit according to claim 1, wherein said configuration information controls said frequency of oscillation and a parameter of said-clock generator.

6. The circuit according to claim 1, wherein said configuration information also controls an output divider.and an output multiplexer.

7. The circuit according to claim 1, wherein said configuration information also controls at least one of (i) an input threshold and (ii) an output drive control of said circuit.

8. The circuit according to claim 1, wherein said configuration information also controls an output divider circuit.

9. The circuit according to claim 1, wherein said clock generator comprises a phase-locked-loop (PLL).

10. The circuit according to claim 1, wherein said single-poly EPROM is programmable after said circuit is packaged.

11. The circuit according to claim 1, wherein said single-poly EPROM is programmable and erasable during a wafer sort step of a production process.

12. A circuit for generating a clock signal comprising:

a single-poly EPROM for storing configuration information to determine a frequency of oscillation of said clock signal; and

a clock generator receiving said configuration information and generating said clock signal having said frequency of oscillation,

wherein said single-poly EPROM and said clock generator are on a single integrated circuit.

13. The circuit according to claim 12, wherein said configuration information comprises frequency based information for determining the frequency at which the clock signal oscillates and general information for controlling one or more non-frequency parameters of the circuit.

14. The circuit according to claim 12, wherein said configuration information comprises frequency based information for determining the frequency at which the clock signal oscillates and general information for controlling two or more non-frequency parameters of the circuit.

15. The circuit according to claim 13, wherein said configuration information controls said frequency of oscillation and an output multiplexer.

16. The circuit according to claim 13, wherein said configuration information controls said frequency of oscillation and a parameter of said clock generator.

17. The circuit according to claim 13, wherein said configuration information also controls an output divider and an output multiplexer.

18. The circuit according to claim 13, wherein said configuration information also controls at least one of (i) an input threshold and (ii) an output drive control of said circuit.

19. The circuit according to claim 13, wherein said configuration information also controls an output divider circuit.

20. The circuit according to claim 13, wherein said clock generator comprises a phase-locked-loop (PLL).

21. The circuit according to claim 13, wherein said single-poly EPROM is programmable after said circuit is packaged.

22. The circuit according to claim 13, wherein said single-poly EPROM is programmable and erasable during a wafer sort step of a production process.

23. A single integrated circuit for generating a plurality of clock output signals each having a frequency, said integrated circuit comprising:

single-poly EPROM configured to store configuration information for determining the frequency of at least one of said plurality of clock signals and one or more non-frequency parameters of said circuit;

a first clock generator having (i) a set of inputs to receive a frequency determining set of said configuration information and (ii) a reference input coupled to a reference output signal, wherein said first clock generator generates one of said plurality of clock output signals at one of said frequencies determined by said configuration information;

a fixed frequency clock generator having a reference input coupled to said reference output signal, said fixed frequency clock generator having an output signal that oscillates at a fixed frequency; and

a multiplexer having (i) a plurality of inputs configured to receive the outputs from said first clock generator and, said fixed frequency clock generator and (ii) a bus input connected to said single-poly EPROM, wherein said multiplexer selects between said outputs from said first clock generator and said fixed frequency clock generator as at least one of said clock output signals in response to one or more bits of the configuration information.

24. The circuit according to claim 23, wherein said first clock generator comprises a phase locked loop and said reference output signal is generated by a crystal oscillator.

25. The circuit according to claim 24, further comprising a second phase locked loop configured to generate another of said plurality of clock output signals.

26. The circuit according to claim 25, further comprising a third phase locked loop configured to generate another of said plurality of clock output signals.

27. The circuit according to claim 24, further comprising a plurality of phase locked loops, each configured to generate one of said plurality of clock output signals.

28. A method for generating a plurality of clock signals comprising the steps of:

(A) storing information in a single-poly EPROM for generating one or more first clock signals having one or more of a plurality of programmable frequencies;

(B) generating a second clock signal having a frequency determined by a crystal or an input having a fixed frequency;

(C) selecting a portion of said information stored in said single-poly EPROM for generating said one or more first clock signals in response to a select input; and

(D) generating said one or more first clock signals in response to said second clock signal and said portion of said information.

29. The method according to claim 28, further comprising the step of:

selecting either one of said first clock signals or said second clock signal to generate one or more third clock signals in response to said information contained in said single-poly EPROM.

30. The method according to claim 29, further comprising the step of:

dividing at least one of said one or more first clock signals or third clock signals in response to said information contained in said single-poly EPROM.

31. The method according to claim 28, wherein said information includes configuration information for configuring non-frequency parameters, said method further comprising the step of:

configuring two or more non-frequency parameters in response to said configuration information.

32. The method according to claim 28, wherein step (A) includes storing configuration information for controlling one or more non-frequency parameters.

33. The method according to claim 32, further comprising the step of:

adjusting one or more operating parameters in response to said configuration information for controlling non-frequency parameters, wherein said one or more operating parameters comprise one or more members of the group consisting of a parameter of a clock generator, an output multiplexer, an output divider, an input threshold level, and an output drive level.

34. A method for generating a plurality of clock signals comprising the steps of:

(A) storing configuration information in a singlepoly EPROM for generating one or more first clock signals having one or more of a plurality of programmable frequencies;

(B) generating a second clock signal having a frequency determined by a crystal or an input having a fixed frequency; and

(C) generating said one or more first clock signals. in response to frequency-determining and non-frequency. configuration information.

35. The method according to claim 34, further comprising the step of:

configuring two or more non-frequency parameters in response to said non-frequency configuration information.