System and method for offset error compensation in comparators

• US 6,433,711 B1
• Filed: 11/09/2000
• Issued: 08/13/2002
• Est. Priority Date: 12/14/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chen, Feng
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): NGUYEN, JOHN B
• Application Number:
  US09/711,349
• Time in Patent Office: 642 Days
• Field of Search: 341/118, 341/172, 341/155, 341/143, 341/128, 341/156, 341/161, 341/129, 341/120, 341/141
• US Class Current: 341/118
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/45968 by offset reduction
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

An offset error compensation system is provided that includes a comparator (42) having an offset error (44), a positive receptor (56), a negative receptor (58), a positive output (60), and a negative output (62). A sequence generator (14) generates control signals (22) representing normal cycles and swap cycles. A first cross connect (46) is coupled to the positive receptor (56), the negative receptor (58), a positive input signal (52), and a negative input signal (54). The first cross connect (46) couples the positive input signal (52) to the positive receptor (56) and the negative input signal (54) to the negative receptor (58) in response to a normal cycle. The first cross connect (46) further couples the positive input signal (52) to the negative receptor (58) and the negative input signal (54) to the positive receptor (56) in response to a swap cycle. A second cross connect (48) is coupled to the positive receptor (56), the negative receptor (58), the positive output (60), and the negative output (62). The second cross connect (48) couples the positive receptor (56) to the positive output (60) and the negative receptor (58) to the negative output (62) in response to the normal cycle. The second cross connect (48) further couples the positive receptor (56) to the negative output (62) and the negative receptor (58) to the positive output (60) in response the swap cycle.

Claims

1. An analog to digital converter, comprising:

a comparator having an offset error, a positive receptor, a negative receptor, a positive output, and a negative output;

a sequence generator operable to generate a control signal representing either a normal cycle or a swap cycle;

a first cross connect coupled to the positive receptor, the negative receptor, a positive input signal, and a negative input signal, the first cross connect operable to couple the positive input signal to the positive receptor and the negative input signal to the negative receptor in response to a normal cycle control signal from the sequence generator, the first cross connect further operable to couple the positive input signal to the negative receptor and the negative input signal to the positive receptor in response to a swap cycle control signal from the sequence generator; and

a second cross connect coupled to the positive receptor, the negative receptor, the positive output, and the negative output, the second cross connect operable to couple the positive receptor to the positive output and the negative receptor to the negative output in response to the normal cycle control signal, the second cross connect further operable to couple the positive receptor to the negative output and the negative receptor to the positive output in response to the swap cycle control signal.

2. The converter of claim 1, wherein the first cross connect is an integral part of the comparator.

3. The converter of claim 1, wherein the second cross connect is an integral part of the comparator.

4. The converter of claim 1, wherein the sequence generator generates an approximately equal number of normal cycle and swap cycle control signals over a period of time.

5. The converter of claim 1, wherein the sequence generator alternates between the normal cycle and the swap cycle for every other control signal.

6. The converter of claim 1, wherein the sequence generator determines a next control signal in response to a comparator output.

7. The converter of claim 1, wherein the sequence generator uses a sigma delta modulator to determine the normal cycle or the swap cycle representation for the control signal.

8. The converter of claim 1, wherein the sequence generator randomizes the control signal representation of the normal cycle and the swap cycle.

9. The converter of claim 1, wherein the positive input signal and the negative input signal comprise a combined input signal.

10. The converter of claim 9, wherein the combined input signal is threshold corrected by removing a threshold voltage from the combined input signal.

11. An analog-to-digital convertor, comprising:

a plurality of comparators, each comparator having an offset error, a positive receptor, a negative receptor, a positive output, and a negative output;

a sequence generator operable to generate a control signal representing either a normal cycle or a swap cycle;

a plurality of first cross connects, each first cross connect coupled to the positive receptor and the negative receptor of one of the plurality of comparators, each first cross connect further coupled to a positive input signal and a negative input signal, each first cross connect operable to couple the positive input signal to the associated positive receptor and the negative input signal to the associated negative receptor in response to a normal cycle control signal generated by the sequence generator, each first cross connect further operable to couple the positive input signal to the associated negative receptor and the negative input signal to the associated positive receptor in response to a swap cycle control signal generated by the sequence generator; and

a plurality of second cross connects, each second cross connect coupled to the positive receptor, the negative receptor, the positive output, and the negative output of one of the plurality of comparators, each second cross connect operable to couple the positive receptor to the positive output and the negative receptor to the negative output in response to the normal cycle control signal, each second cross connect further operable to couple the positive receptor to the negative output and the negative receptor to the positive output in response to the swap cycle control signal.