Methods, apparatuses, and systems for sampling or pulse generation

• US 6,433,720 B1
• Filed: 06/06/2001
• Issued: 08/13/2002
• Est. Priority Date: 03/06/2001
• Status: Expired due to Term

• Current Assignee: Furaxa, Inc.
• Original Assignee: Furaxa, Inc.
• Inventors: Chacko, Steven J., Libove, Joel M.
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US09/876,016
• Time in Patent Office: 433 Days
• Field of Search: 341/144, 341/145, 341/152, 341/156
• US Class Current: 341/144
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

A method and apparatus for generating ultra-fast (picosecond-range) electrical sampling apertures and pulses, requiring only a single transition of a control signal, is disclosed. Implemented in a novel circuit architecture that is suited to fabrication as a low-cost monolithic integrated circuit, the method produces more stable, more reproducible, and more precisely shaped sampling apertures and pulses, with lower power usage and cost, than conventional techniques. The combination of speed and reproducibility enabled by the invention allows the integration of large numbers of virtually identical fast sampling apertures or pulse generators on a single IC, enabling single-shot capture of such a rapid sequence of samples that even a single cycle of a very fast, microwave frequency, electronic waveform may be precisely sampled at multiple points.

Claims

1. A sampler/pulser circuit comprising:

a differential pair having control terminals coupled to input terminals to receive a data input signal;

level activated switching elements coupled to the differential pair, the level activated switching elements responsive to a first voltage level and a second voltage level; and

a control input coupled to the level activated switching elements, the control input to activate the level switching elements to sample the data input signal or generate a pulse responsive thereto when a voltage level of the control input is between the first voltage level and the second voltage level.

2. The sampler/pulser circuit of claim 1 wherein,

the first voltage level is greater than the second voltage level, and

the control input activates the level switching elements to sample the data input signal or generate a pulse responsive thereto when the voltage level of the control input transitions from being greater than to less than the first voltage level and deactivates the level switching elements when the voltage level of the control input transitions from being greater than to less than the second voltage level.

3. The sampler/pulser circuit of claim 1 wherein,

the first voltage level is greater than the second voltage level, and

the control input activates the level switching elements to sample the data input signal or generate a pulse responsive thereto when the voltage level of the control input transitions from being less than to greater than the second voltage level and deactivates the level switching elements when the voltage level of the control input transitions from being less than to greater than the first voltage level.

4. The sampler/pulser circuit of claim 1 wherein,

the level switching elements are differentially paired transistors.

5. The sampler/pulser circuit of claim 1 wherein,

the level switching elements are differentially paired diodes.

6. A circuit comprising:

a first transistor and a second transistor providing a differential input stage, the first transistor and the second transistor having control terminals coupled to input terminals to receive a data input signal and source terminals coupled to a current source;

a third transistor and a fourth transistor each having control terminals coupled together and to a first voltage level, the third transistor and the fourth transistor each having a source terminal coupled to the drain terminal of the first transistor and the second transistor respectively;

a fifth transistor and a sixth transistor each having control terminals coupled together and to a control signal, the fifth transistor and the sixth transistor each having a source terminal coupled to the drain terminal of the third transistor and the fourth transistor respectively;

a seventh transistor and an eighth transistor each having control terminals coupled together and to a third voltage level, the seventh transistor and the eighth transistor each having a source terminal coupled to the drain terminal of the fifth transistor and the sixth transistor respectively, the seventh transistor and the eighth transistor each having a drain terminal coupled to a first and second output terminal respectively of a differential output; and

a first resistor and a second resistor each having one end coupled to a power supply and an opposite end coupled to the drain terminal of the seventh transistor and the eighth transistor respectively and the first and second output terminal respectively.

7. The circuit of claim 6 wherein,

the third, fourth, fifth, sixth, seventh, and eighth transistors are level-activated switching elements responsive to the first voltage level, the third voltage level, and the control signal.

8. The circuit of claim 7 wherein,

the control signal activates the level switching elements to sample the data input signal or generate a pulse responsive thereto when a voltage level of the control signal is between the first voltage level and the third voltage level.

9. The circuit of claim 6 further comprising:

a third resistor and a fourth resistor each having having one end coupled to the power supply and an opposite end coupled to the drain terminal of the fifth transistor and the sixth transistor respectively and the source terminal of the seventh transistor and the eighth transistor respectively.

10. The circuit of claim 6 further comprising:

a capacitor having one end coupled to the first out put terminal and another end coupled to the second output terminal.

11. The circuit of claim 6 further comprising:

a ninth transistor and a tenth transistor each having control terminals coupled together and to the control signal and each having a source terminal coupled to the drain terminal of the fifth transistor and the sixth transistor respectively and the source terminal of the seventh transistor and the eighth transistor respectively, and each having a drain terminal coupled together and to the power supply.

12. The circuit of claim 6 further comprising:

an eleventh transistor and a twelfth transistor each having control terminals coupled together and to a second voltage level and each having a source terminal coupled to the source terminal of the fifth transistor and the sixth transistor respectively and the drain terminal of the third transistor and the fourth transistor respectively, and each having a drain terminal coupled together and to the power supply.

13. The circuit of claim 6 wherein,

the transistors are one of Gallium Arsenide (GaAs) MESFET, GaAs Heterojunction Bipolar Transistor (HBT), GaAs High Electron Mobility Transistor (HEMT), Indium Phosphide (InP) transistor, Silicon-Germanium (SiGe), Silicon bipolar or MOS transistors.

14. A method comprising:

providing a control signal changing from a first voltage level to a second voltage level;

sampling a data input signal in response to a change in the voltage level of the control signal between the first voltage level and the second voltage level; and

maintaining the sample of the data signal in response to the voltage level of the control signal being outside a range of voltage levels between the first voltage level and the second voltage level.

15. The method of claim 14 wherein,

the sampling of the data input signal initiates at a first switching point and ends at a second switching point between the range of voltage levels between the first voltage level and the second voltage level.

16. A method comprising:

providing a control signal changing from a first voltage level to a second voltage level;

generating a pulse in an output signal in response to a change in the voltage level of the control signal between the first voltage level and the second voltage level; and

maintaining a steady state in the output signal in response to the voltage level of the control signal being outside a range of voltage levels between the first voltage level and the second voltage level.

17. The method of claim 16 wherein,

the generating of the pulse in the output signal initiates at a first switching point and ends at a second switching point between the range of voltage levels between the first voltage level and the second voltage level.

18. A sampler/pulser circuit comprising:

a differential pair having control terminals coupled to input terminals to receive a data input signal;

level activated switching elements coupled to the differential pair, the level activated switching elements responsive to a first voltage level and a second voltage level; and

differential control inputs coupled to the level activated switching elements including a positive control signal and a negative control signal, the differential control inputs to activate the level switching elements to sample the data input signal or generate a pulse responsive thereto when a voltage level of the positive control signal is between a first switch point and a second switch point.

19. The sampler/pulser circuit of claim 18 wherein,

the first voltage level is greater than the second voltage level, and

the differential control inputs activate the level switching elements to sample the data input signal or generate a pulse responsive thereto when the voltage level of the positive control signal is between the first switch point and the second switch point and deactivates the level switching elements when the voltage level of the positive control signal is outside of the first switch point and the second switch point.

20. The sampler/pulser circuit of claim 18 wherein,

the level switching elements are differentially paired transistors.

21. The sampler/pulser circuit of claim 18 wherein,

the level switching elements are differentially paired diodes.

22. A circuit comprising:

a first transistor and a second transistor providing a differential input stage, the first transistor and the second transistor having control terminals coupled to input terminals to receive a data input signal and source terminals coupled to a current source;

a third transistor and a fourth transistor each having control terminals coupled together and to a first voltage level, the third transistor and the fourth transistor each having a source terminal coupled to the drain terminal of the first transistor and the second transistor respectively;

a first diode and a second diode each having a cathode terminal coupled to the drain terminal of the third transistor and the fourth transistor respectively;

a third diode and a fourth diode each having a cathode terminal coupled to an anode terminal of the first diode and the second diode respectively;

a fifth diode and a sixth diode each having a cathode terminal coupled to the drain terminal of the third transistor and the fourth transistor respectively and each having an anode terminal coupled to a second voltage level;

a first resistor and a second resistor each having one end coupled to a power supply and an opposite end coupled to an anode terminal of the third diode and the fourth diode respectively and the first and second output terminals respectively; and

a third resistor and a fourth resistor each having one end coupled to a control signal, the third resistor having an opposite end coupled to the anode terminal of the first diode and the cathode terminal of the third diode and the fourth resistor having an opposite end coupled to the anode terminal of the second diode and the cathode terminal of the fourth diode.

23. The circuit of claim 22 wherein,

the third and fourth transistors and the first through sixth diodes are level-activated switching elements responsive to the first voltage level, the second voltage level, and the control signal.

24. The circuit of claim 23 wherein,

the control signal activates the level switching elements to sample the data input signal or generate a pulse responsive thereto when a voltage level of the control signal is between the first voltage level and the second voltage level.

25. The circuit of claim 22 further comprising:

a capacitor having one end coupled to the first output terminal and another end coupled to the second output terminal.

26. The circuit of claim 22 wherein,

the transistors are one of Gallium Arsenide (GaAs) MESFET, GaAs Heterojunction Bipolar Transistor (HBT), GaAs High Electron Mobility Transistor (HEMT), Silicon-Germanium (SiGe), Indium Phosphide (InP), Silicon bipolar or MOS transistors.

27. A method comprising:

providing a control signal transitioning between first voltage levels and second voltage levels;

generating a first pulse in an output signal in response to a transition in the control signal from the first voltage level to the second voltage level; and

generating a second pulse in the output signal in response to a transition in the control signal from the second voltage level to the first voltage level.

28. The method of claim 27 further comprising:

maintaining a steady state in the output signal in response to the voltage level of the control signal being outside a range of voltage levels between the first voltage level and the second voltage level.

29. The method of claim 27 wherein,

the generating of the first pulse in the output signal initiates at a first switching point and ends at a second switching point between the first voltage level and the second voltage level.

30. The method of claim 27 wherein,

the generating of the second pulse in the output signal initiates at a second switching point and ends at a first switching point between the second voltage level and the first voltage level.

31. A method in a circuit without differentiating circuit elements and without pulse reversing elements comprising:

providing an electrical control signal;

generating an output signal having two transitions in response to a single transition of the electrical control signal;

wherein a first transition of the two transitions in the output signal is a rise of the output signal from an initial operating voltage to a second voltage; and

wherein the second transition of the two transitions in the output signal is a fall of the output signal to the initial operating voltage.

32. The method of claim 31 wherein,

the differentiating circuit elements are capacitors.

33. The method of claim 31 wherein,

the pulse reversing elements are transmission lines or delay lines.

34. A method in a circuit without differentiating circuit elements and without pulse reversing elements comprising:

providing a control signal;

in response to a single transition in the control signal, momentarily conveying to one or more output terminals a voltage proportional to the voltage on one or more respective input terminals; and

wherein the voltage conveyed to the one or more output terminals is proportional to the voltage on the one or more respective input terminals during a period of time when the single transition occurs in the control signal.

35. The method of claim 34 wherein,

the differentiating circuit elements are capacitors.

36. The method of claim 34 wherein,

the pulse reversing elements are transmission lines or delay lines.

37. The method of claim 34 further comprising:

holding on the one or more output terminals the voltage conveyed thereto after completion of the single transition in the control signal the differentiating circuit elements are capacitors.

38. The method of claim 37 wherein,

the holding is provided by a conventional electrical storage means.

39. The method of claim 38 wherein,

the conventional electrical storage means is a capacitor.

40. A signal processing system comprising:

a first string of a plurality of analog delay lines coupled in series together, a first analog delay line of the first string to receive a data input signal and the first string of the plurality of analog delay lines to generate delayed data input signals;

a plurality of sampler circuits, a first sampler circuit to receive the data input signal and the other sampler circuits to receive the respective delayed data input signals to generate samples of a cycle of a waveform of the data input signal, each of the plurality of sampler circuits including level activated switching elements to sample the data input signal and the respective delayed data input signals on a transition of a clock signal at one time;

signal processing circuitry coupled to the outputs of the plurality of sampler circuits to process the samples of the cycle of the waveform of the data input signal; and

a second string of a plurality of analog delay lines coupled in series together, each respective analog delay line of the second string of the plurality of analog delay lines responsive to the processed samples of the cycle of the waveform of the data input signal and to generate an output signal.

41. The signal processing system of claim 40 wherein,

the signal processing circuitry is a plurality of analog multipliers coupled to the plurality of sampler circuits to multiply a respective coefficient with each respective sample of the cycle of the waveform of the data input signal.

42. The signal processing system of claim 40 further comprising:

a plurality of pulser circuits coupled between the outputs of the signal processing circuitry and the second string of the plurality of analog delay lines, each respective pulser circuit to receive the processed sample and generate a pulsed output in response thereto.

43. A waveform generating system comprising:

a microprocessor to generate a plurality of digital signals corresponding to a desired shape of a waveform;

a plurality of digital to analog converters coupled to the microprocessor, each of the plurality of digital to analog converters to receive one of the plurality of digital signals to generate a corresponding analog level;

a plurality of samplers/pulsers coupled to the plurality of digital to analog converters, each of the plurality of samplers/pulsers to receive the respective analog level and generate a pulse in response thereto upon receiving a transition in a control signal;

a string of a plurality of analog delay lines coupled in series together and coupled to the plurality of samplers/pulsers, each analog delay line in the string of the plurality of analog delay lines to receive a respective pulse from the plurality of samplers/pulsers and generate an output waveform at one end of the string of the plurality of analog delay lines.

44. The waveform generating system of claim 43 wherein,

one of the plurality of samplers/pulsers couples to an output terminal to generate the output waveform, and

one of the analog delay lines in the string of the plurality of analog delay lines couples to the output terminal and the one of the plurality of samplers/pulsers to generate the output waveform.

45. The waveform generating system of claim 43 wherein,

each of the plurality of samplers/pulsers include level activated switching elements to generate a pulse in response to the respective analog level during the transition of the control signal at the same time.