DRAM module and method of using SRAM to replace damaged DRAM cell

• US 6,434,033 B1
• Filed: 11/30/2000
• Issued: 08/13/2002
• Est. Priority Date: 11/30/2000
• Status: Expired due to Fees

• Current Assignee: Pien Chien
• Original Assignee: Pien Chien
• Inventors: Chien, Pien
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/726,473
• Publication Number:
  US 20020064073A1
• Time in Patent Office: 621 Days
• Field of Search: 365/49, 365/200, 365/201, 365/149, 365/154
• US Class Current: 365/49.1
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

A DRAM module and a method of replacing a damaged DRAM cell in the DRAM module with a SRAM. The DRAM module has at least a non-volatile memory and a DRAM control logic circuit. In the process of replacing the damaged DRAM with the SRAM, the damaged address data is compared to DRAM address data. If the data are consistent, the address of the SRAM is used to access data. Meanwhile, the output enabling signal of the DRAM cell is turned off. It can thus assist the computer to correctly find the good DRAM cell for data access, so as to ensure a normal operation of the computer.

Claims

1. A DRAM module using a SRAM to replace a damaged DRAM cell, the DRAM module coupled to a system bus and being activated by a power up signal, comprising:

a damaged address recorder, to pre-store a plurality of damaged address data, and to output the damaged address data by a power up signal;

a content addressable memory, coupled to the damaged address recorder, to write the damaged address data therein, and to receive a DRAM address data to compare to the damaged address data to output a match signal;

a SRAM, coupled to the content addressable memory to receive the match signal, and to access a data signal according to the match signal and a DRAM control signal;

a DRAM, coupled to the content addressable memory to receive the match signal and the DRAM address data, and to access the data signal according to the match signal, the DRAM address signal and the DRAM control signal; and

a DRAM control logic circuit, coupled to the system bus, the content addressable memory, the DRAM control signal and the data signal, to perform one of the following operations;

data signal access in the SRAM;

data signal access in the DRAM; and

data written into the content addressable memory.

2. The DRAM module according to claim 1, wherein the damaged address recorder comprises a flash memory.

3. The DRAM module according to claim 1, wherein the damaged address recorder comprises an electrically erasable programmable read only memory.

4. The DRAM module according to claim 1, wherein the damaged address recorder comprises an electrically programmable read only memory.

5. The DRAM module according to claim 1, wherein the damaged address recorder comprises a programmable logic array.

6. The DRAM module according to claim 1, wherein the damaged address recorder comprises a programmable fuse.

7. The DRAM module according to claim 1, wherein the damaged address data are written in the content addressable memory by a software.

8. The DRAM module according to claim 1, wherein when the DRAM address data is the same as one of the damaged address data, the match signal is activated to enable a certain address of the SRAM, and to disable an output enabling signal of the DRAM.

9. The DRAM module according to claim 1, wherein when the DRAM address data is not the same as any of the damaged address data, the match signal is disabled, so that the DRAM is operated normally without enabling the SRAM.

10. The DRAM module according to claim 1, wherein the damaged address data provides a parity bit to determine whether the damaged address data are either valid or invalid data.

11. The DRAM module according to claim 10, wherein when the damaged address data are invalid data, the parity bit disables the match signal.

12. A method of using a SRAM to replace a damaged DRAM cell, comprising comparing a plurality of damaged address data with a DRAM address data, so as to output a match data to enable a certain address in the SRAM, and to disable an output enabling signal of the DRAM, wherein step of comparison is executed by a content addressable memory.

13. The method according to claim 12, wherein the DRAM is operated normally when the DRAM address data is different from any of the damaged address data.

14. An apparatus using a SRAM to replace a damaged DRAM cell, coupled to a SRAM, a DRAM and a system bus, the apparatus comprising:

a damaged address recorder, to pre-store a plurality of damaged address data;

a content addressable memory, coupled to the damaged address recorder, the SRAM and the DRAM, to compare the damaged address data with a DRAM address data to output a match signal; and

a DRAM control logic circuit, coupled to the system bus, the content addressable memory, the DRAM and the SRAM, to receive the DRAM address data, a DRAM control signal and a data signal, to perform one of the following operations;

data signal processing in the SRAM;

data signal processing in the DRAM; and

writing the data signal in the content addressable memory.

15. The apparatus according to claim 14, wherein the damaged address data comprises a flash memory.

16. The apparatus according to claim 14, wherein damaged address data comprises an electrically erasable programmable read only memory.

17. The apparatus according to claim 14, wherein the damaged address data comprises an electrically programmable read only memory.

18. The apparatus according to claim 14, wherein the damaged address data comprises a programmable logic array.

19. The apparatus according to claim 14, wherein the damaged address data comprises a programmable fuse.

20. The apparatus according to claim 14, wherein the damaged address data are written into the content addressable memory by a software.

21. The apparatus according to claim 14, wherein when the DRAM address data is the same as one of the damaged address data, the match signal is activated to enable a certain address of the SRAM, and an output enabling signal of the DRAM is disabled.

22. The apparatus according to claim 14, wherein when the DRAM address signal is different from any of the damaged address data, the match signal is disabled, the SRAM is not enabled, and the DRAM is operated normally.

23. The apparatus according to claim 14, wherein the damaged address data provide a parity bit to determine whether the damaged address data are valid or invalid data.

24. The apparatus according to claim 14, wherein the parity bit disable the match signal when the damaged address data are invalid.

25. An apparatus using a SRAM to replace a damaged DRAM cell, coupled to a SRAM, a DRAM and a system bus, the apparatus comprising:

an address recorder, to pre-store a plurality of damaged address data;

a content addressable memory, coupled to the address recorder, the SRAM and the DRAM, to compare the damaged address data with a DRAM address data to output a match signal; and

a DRAM control logic circuit, coupled to the system bus, the content addressable memory, the DRAM and the SRAM, to receive the DRAM address data a DRAM control signal and a data signal.

26. The apparatus according to claim 25, wherein, the DRAM control logic circuit at least perform one of the following operations:

data signal processing in the SRAM;

data signal processing in the DRAM; and

writing the data signal in the content addressable memory.

27. An apparatus comprising means for identifying a plurality of address data by their content, means for comparing a plurality of damaged address data with a DRAM address data, and means for generating at least a signal for disabling at least one output enabling signal in response to a match of one of the damaged address data with the DRAM address data.

28. A method of using a SRAM to replace a damaged DRAM cell, comprising:

identifying a plurality of address data by their content;

comparing a plurality of damaged address data with a DRAM address data; and

generating at least a signal for disabling at least one output enabling signal in response to a match of one of the damaged address data with the DRAM address data.

29. A method of using a SRAM to replace a damaged DRAM cell, comprising:

pre-storing a plurality of damaged address data into an address recorder; and

coupling the address recorder a content addressable memory, the SRAM and the DRAM, wherein the damaged address data is compared with a DRAM address data using the content addressable memory to output a match signal.