Nonvolatile semiconductor memory device and method of operation thereof

• US 6,434,053 B1
• Filed: 12/05/2000
• Issued: 08/13/2002
• Est. Priority Date: 12/06/1999
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Fujiwara, Ichiro
• Primary Examiner(s): Ho, Hoai V.
• Application Number:
  US09/729,214
• Publication Number:
  US 20020097621A1
• Time in Patent Office: 616 Days
• Field of Search: 365/185.28, 365/185.03, 365/185.17, 365/185.26, 365/185.01, 257/324
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A MONOS type memory transistor increased in injection efficiency or storing a plurality of bits of data by local injection of a charge into part of a plane area of distribution of a charge storing means, comprised of a channel forming region of a first conductivity type, source and drain regions of a second conductivity type, gate insulating films formed on the channel forming region, gate electrodes, and a charge storing means (charge traps) formed in the gate insulating film and dispersed in a plane facing the channel forming region and the thickness direction and in which hot electrons caused by a band-to-band tunneling current are injected from the source and drain regions, where in the gate insulating film, between a first storage region and a second storage region into which electrons are locally injected, there is a third region into which hot electrons are not injected.

Claims

1. A nonvolatile semiconductor memory device comprising:

a channel forming region comprised of a first conductivity type semiconductor,

source and drain regions comprised of a second conductivity type semiconductor sandwiching the channel forming region between them,

a gate insulating film provided on said channel forming region,

a gate electrode provided on said gate insulating film, and

a charge storing means which is formed in said gate insulating film dispersed in the plane facing said channel forming region and in the direction of thickness and is injected with hot electrons at the time of operation from said source and drain regions,

wherein a memory transistor comprises said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode has a gate length shorter than or equal to the gate length when a region retaining hot electrons from one of said source and drain regions is merged or partially merged in the gate insulating film with a region retraining hot electrons from the other of said source and drain regions when hot electrons are injected from both said source and drain regions.

2. The nonvolatile semiconductor memory device as set forth in claim 1, wherein said hot electrons are those caused by a band-to-band tunneling current.

3. The nonvolatile semiconductor memory device as set forth in claim 1, wherein said gate insulating film comprises a storage region holding the hot electrons injected from said source and drain regions and another region not injected by the hot electrons.

4. The nonvolatile semiconductor memory device as set forth in claim 3, wherein

said gate insulating film comprises

a first storage region holding the hot electrons injected from either said source region or said drain region,

a second storage region holding the hot electrons injected from the other of said source and drain regions, and

a third region between the first and the second regions into which the hot electrons are not injected.

5. The nonvolatile semiconductor memory device as set forth in claim 4, wherein

a charge storing means is formed in the first and the second storage region and

the region of distribution of said charge sorting means is spatially separated by the third region.

6. The nonvolatile semiconductor memory device as set forth in claim 5, wherein

said first and second storage regions are stacked film structures comprised of a number of films stacked together, and

said third region is a single layer of a dielectric.

7. The nonvolatile semiconductor memory device as set forth in claim 5, wherein

the gate electrode comprises

a first gate electrode formed on the first storage region,

a second gate electrode formed on the second storage region, and

a third gate electrode formed on the third region and

said first, second, and third gate electrodes are spatially separated from each other.

8. The nonvolatile semiconductor memory device as set forth in claim 7, wherein said channel forming region comprises two channel forming regions of two memory transistors and a channel forming region of a control transistor between and in connection with the former two channel forming regions.

9. The nonvolatile semiconductor memory device as set forth in claim 7, wherein

a plurality of memory transistors each comprises a channel forming region, source and drain regions, gate insulating film, and gate electrode are arranged in the word line direction and in the bit line direction;

in the memory transistors in the word line direction, said first and second gate electrodes are commonly connected through word lines; and

in the memory transistors in the bit line direction, said third gate electrodes are commonly connected.

10. The nonvolatile semiconductor memory device as set forth in claim 4, further comprising

a first gate electrode at the outer side of the first storage region, and

a second gate electrode at the outer side of the second storage region,

said first and second gates being spatially separated by a single said gate electrode formed on said first storage region, said second storage region, and said third region.

11. The nonvolatile semiconductor memory device as set forth in claim 1, wherein said first conductivity type is an n-type, and said second conductivity type is a p-type.

12. The nonvolatile semiconductor memory device as set forth in claim 1, wherein

a plurality of memory transistors each of which includes said channel forming region, said source and drain regions, and gate insulating film, and said gate electrode, are arranged in both a word line direction and a bit line direction;

said memory device further comprises

a plurality of word lines and

a plurality of common lines which intersect with said plurality of word lines in an electrically insulated state;

the plurality of said gate electrodes are respectively connected to said plurality of word lines; and

the plurality of said source and drain regions are coupled with the plurality of common lines.

13. The nonvolatile semiconductor memory device as set forth in claim 12, comprising

word lines commonly connecting said gate electrodes in a word line direction,

first common lines commonly connecting one of said source and drain regions in a bit line direction, and

second common lines commonly connecting the other of said source and drain regions.

14. The nonvolatile semiconductor memory device as set forth in claim 13, wherein

said first common lines include

first sub-lines commonly connecting one of said source and drain regions in a bit line direction and

first main lines commonly connecting the first sub-lines in a bit line direction;

said second common lines include

second sub-lines commonly connecting the other of said source and drain regions and

second main lines commonly connecting the second sub-lines; and

said plurality of memory transistors are connected in parallel between said first sub-lines and the second sub-lines.

15. The nonvolatile semiconductor memory device as set forth in claim 1, wherein

a plurality of memory transistors each of which includes said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode, are arranged in both a word line direction and a bit line direction;

said source and drain regions comprises a semiconductor doped with the second conductivity type impurity, and

an element isolation layer is formed between one of said source and drain regions in one said memory transistor and the other of said source and drain regions in another said memory transistor adjacent to the former in the word line direction.

16. The nonvolatile semiconductor memory device as set forth in claim 1, wherein

said charge storing means does not have conductivity as a plane as a whole facing said channel forming region at least when there is not dissipation of charges in the outside.

17. The nonvolatile semiconductor memory device as set forth in claim 16, wherein said gate insulating film comprises

a bottom insulating film on said channel forming region, and

a nitride film or an oxynitride film on said bottom insulating film.

18. The nonvolatile semiconductor memory device as set forth in claim 16, wherein said gate insulating film comprises

a bottom insulating film on said channel forming region, and

mutually insulated small particle conductors formed on the bottom film and functioning as said charge storing means.

19. The method of operating a nonvolatile semiconductor memory device comprising:

a channel forming region comprised of a first conductivity type semiconductor, source and drain regions comprised of a second conductivity type semiconductor with said channel forming region in between, a gate insulating film provided on said channel forming region and including inside it a charge storing means dispersed in a plane facing said channel forming region and thickness direction, and a gate electrode provided on the gate insulating film;

said method comprising a step of injecting hot electrons into said charge storing means from said source and drain regions when writing data to the device,

wherein the gate length of a memory transistor including said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode is shorter than or equal to the gate length when said source and drain regions retaining hot electrons are merged or partially merged in the gate insulating film.

20. The method of operating a nonvolatile semiconductor memory device as set forth in claim 19, comprising, in the write operation, a step of injecting hot electrons caused by the band-to-band tunneling current into said charge storing means from said source and drain regions.

21. The method of operating a nonvolatile semiconductor memory device as set forth in claim 19, comprising, in a write operation, a step of injecting hot electrons into part of the region of distribution of said charge storing means in said gate insulating film.

22. The method of operating a nonvolatile semiconductor memory device as set forth in claim 20, comprising, in a write operation, a step of:

injecting hot electrons into a first storage region from one of said source and drain regions; and

injecting hot electrons from the other of said source and drain regions into a second storage region separated from the first storage region in the gate insulating film independently from the injection of hot electrons to said first storage region.

23. The method of operating a nonvolatile semiconductor memory device as set forth in claim 22, wherein:

said gate insulating film has a third region, between the first and the second storage regions, into which hot electrons are not injected;

said charge storing means is formed in said first and second storage regions; and

the region of distribution of said charge storing means is spatially separated by said third region.

24. The method of operating a nonvolatile semiconductor memory device as set forth in claim 23, wherein;

said first and second storage regions are of stacked film structures comprising a plurality of films stacked on each other, and

said third region is an insulating film of a single material.

25. The method of operating a nonvolatile semiconductor memory device as set forth in claim 23, wherein

in write operation of a memory cell array comprised of a plurality of said memory transistors each including said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode, arranged in both a word line direction and bit line direction wherein said gate electrodes are commonly connected through word lines for every certain number of memory transistors in a word line direction,

said method comprising in a write operation for all memory transistors connected to the same word line, step of:

applying a specified voltage to all of the source and drain regions corresponding to the first and the second storage regions into which hot electrons are injected;

setting the source and drain regions correspond to the first and the second storage regions into which hot electrons injected in an electrically floating state;

applying a write voltage, which is equal to a predetermined difference with said specified voltage applied to said source and drain regions, on said same word line; and

writing all memory transistors connected to said same word line in parallel with one operation.

26. The method of operating a nonvolatile semiconductor memory device as set forth in claim 25, wherein:

said source and drain regions are comprised of a semiconductor doped with the second conductivity type impurity; and

said memory cell array is provided with an element isolation layer between one of said source and drain regions in one said memory transistor and the other of said source and drain regions in another said memory transistor adjacent to the former in the word line direction.

27. The method of operating a nonvolatile semiconductor memory device as set forth in claim 19, wherein

the region retaining hot electrons from one of said source and drain regions is merged or partially merged in the gate insulating film with the region retaining hot electrons from the other of said source and drain regions.

28. The method of operating a nonvolatile semiconductor memory device as set forth in claim 19, comprising, when writing data, a step of

applying a specified write voltage between said source and drain regions and said gate electrode.

29. The method of operating a nonvolatile semiconductor memory device as set forth in claim 28, wherein:

a memory cell array comprised of a plurality of said memory transistors arranged in both a word line direction and bit line direction;

said gate insulating film in each said memory transistor each including said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode comprises a first storage region into which hot electrons are injected from one of said source and drain regions, a second storage region into which hot electrons are injected from the other of said source and drain regions, and a third region which is between said first and the second regions and into which to electrons are not injected; and

said gate electrode in said memory transistor comprises a first gate electrode formed on said first storage region, a second gate electrode formed on said second storage region, and a third gate electrode formed on said third region,

said method comprising, when writing data to one region of said first and the second storage regions, a step of setting the gate electrode at the other of said first and second storage regions electrically floating, or applying a voltage of 0V or of an opposite polarity relative to said channel forming region to the gate electrode at the other of said first and the second storage regions.

30. The method of operating a nonvolatile semiconductor memory device as set forth in claim 28, said device having

memory cell array comprised of a plurality of memory transistors each including said channel forming region, and source and drain regions, said gate insulating film and said gate electrode arranged in both a word line direction and bit line direction wherein said gate electrodes are commonly connected through the word lines for every certain number of memory transistors in a word line direction,

said method comprising, in a write operation, a step of

applying a voltage of 0V or of an opposite polarity relative to said channel forming region to the nonselected word lines to which a memory transistor to be operated is not connected.

31. The method of operating a nonvolatile semiconductor memory device as set forth in claim 19, wherein:

a memory cell array comprised of a plurality of a memory transistors each including said channel forming region, and source and drain regions, said gate insulating film, and said gate electrode arranged in both a word line direction and bit line direction;

one of said source and drain regions are commonly connected through first common lines for every certain number of memory transistors in a bit line direction; and

the other of said source and drain regions are commonly connected through second common lines,

said method comprising step of;

applying a specified voltage to the first and/or the second common lines to which the memory transistor to be operated is connected; and

applying a voltage of 0V or of an polarity opposite to said specified voltage to the first and the second common lines to which the memory transistor to be operated is not connected.

32. The method of operating a nonvolatile semiconductor memory device as set forth in claim 19, wherein:

in a read operation of said nonvolatile semiconductor memory device wherein

said gate insulating film in said memory transistor including said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode

said gate insulating film comprises a first storage region into which hot electrons are injected from one of said source and drain regions, a second storage region into which hot electrons are injected from the other of said source and drain regions, and a third region which is between said first and the second regions and into which hot electrons are not injected; and

said gate electrode in said memory transistor comprises a first gate electrode formed on said first storage region, a second gate electrode formed on said second storage region, and a third gate electrode formed on said third region,

said method comprising, in a read operation, steps of;

applying a specified read drain voltage between said source and drain regions so that the storage region to be read becomes the source;

applying a specified voltage to said third gate electrode; and

applying a specified read gate voltage of the same polarity as that applied to said third gate electrode to said first and/or the second gate electrodes.

33. The method of operating a nonvolatile semiconductor memory device as set forth in claim 19, comprising,

when erasing data, a step of extracting hot electrons which are injected from said source and drain regions and are stored in said charge storing means to the side of said source and drain regions by utilizing the direct tunneling effect or the FN tunneling effect.

34. The method of operating a nonvolatile semiconductor memory device as set forth in claim 19, comprising,

when erasing data, a step of extracting hot electrons which are injected from said source and drain regions and are separated and stored at the two sides of the charge storing means in the channel direction to the substrate side separately or simultaneously by utilizing the direct tunneling effect or the FN tunneling effect.

35. The method of operating a nonvolatile semiconductor memory device as set forth in claim 19, wherein

said first conductivity type is an n-type, and said second conductivity type is a p-type.

36. The method of operating a nonvolatile semiconductor memory device as set forth in claim 19, wherein

said charge storing means does not have conductivity as a plane as a whole facing said channel forming region at least when there is not dissipation of charges in the outside.

37. The method of operating a nonvolatile semiconductor memory device as set forth in claim 36, wherein said gate insulating film comprises:

a bottom insulating film on said channel forming region; and

a nitride film or an n oxynitride film on said bottom insulating film.

38. The method of operating a nonvolatile semiconductor memory device as set forth in claim 36, wherein said gate insulating film comprises:

a bottom insulating film on said channel forming region; and

mutually insulated small particle conductors formed on the bottom film and functioning as said charge storing means.

39. A nonvolatile semiconductor memory device comprising:

a channel forming region comprised of a first conductivity type semiconductor,

source and drain regions comprised of a second conductivity type semiconductor sandwiching the channel forming region between them,

a gate insulating film provided on said channel forming region, said gate insulating film comprising a first storage region holding hot electrons injected from either said source region or said drain region, a second storage region holding hot electrons injected form the other of said source and drain regions, and a third region between the first and the second regions into which hot electrons are not injected, said third region comprising a single layer of a dielectric,

a gate electrode provided on said gate insulating film, and

a charge storing means which is formed in said gate insulating film dispersed in the plane facing said channel forming region and in the direction of thickness and is injected with hot electrons at the time of operation from said source and drain regions.

40. The nonvolatile semiconductor memory device as set forth in claim 39, wherein said hot electrons are those caused by a band-to-band tunneling current.

41. The nonvolatile semiconductor memory device as set forth in claim 39, wherein said charge storing means is formed in the first and the second storage regions and the region of distribution of said charge storing means is spatially separated by the third region.

42. The nonvolatile semiconductor memory device as set forth in claim 39, wherein said first and the second storage regions are stacked film structures comprised of a number of films stacked together.

43. The nonvolatile semiconductor memory device as set forth in claim 39, wherein the gate electrode comprises a first gate electrode formed on the first storage region, a second gate electrode formed on the second storage region, and a third gate electrode formed on the third region and said first, second, and third gate electrodes are spatially separated from each other.

44. The nonvolatile semiconductor memory device as set forth in claim 39, wherein said channel forming region comprises two channel forming regions of two memory transistors and a channel forming region of a control transistor between and in connection with the former two channel forming regions.

45. The nonvolatile semiconductor memory device as set forth in claim 39, wherein a plurality of memory transistors each comprise a channel forming region, source and drain regions, gate insulating film, and gate electrode are arranged in the word line direction and in the bit line direction;

in the memory transistors in the word line direction, said first and second gate electrodes are commonly connected through word lines; and

in the memory transistors in the bit line direction, said third gate electrodes are commonly connected.

46. The nonvolatile semiconductor memory device as set forth in claim 39, further comprising a first gate electrode at the outer side of the first storage region, and a second gate electrode at the outer side of the second storage region, and first and second gates being spatially separated by a single said gate electrode formed on said first storage region, and second storage region, and said third region.

47. The nonvolatile semiconductor memory device as set forth in claim 39, wherein a memory transistor comprises said channel forming region, said source and drain regions, and gate insulating film, and said gate electrode has a gate length shorter than or equal to the gate length when a region retaining hot electrons from one of said source and drain regions is merged or partially merged in the gate insulating film with a region retaining hot electrons from the other of said source and drain regions when hot electrons are injected from both said source and drain regions.

48. The nonvolatile semiconductor memory device as set forth in claim 39, wherein said first conductivity type is an n-type, and said second conductivity type is a p-type.

49. The nonvolatile semiconductor memory device as set forth in claim 39, wherein a plurality of memory transistors each of which includes said channel forming region, said two source and drain regions, said gate insulating film, and said gate electrode, are arranged in both a word line direction and a bit line direction;

said memory device further comprises;

a plurality of word lines and

a plurality of common lines which intersect with said plurality of word lines in an electrically insulated state;

the plurality of said gate electrodes are respectively connected to said plurality of word lines; and

the plurality of said source and drain regions are coupled with the plurality of common lines.

50. The nonvolatile semiconductor memory device as set forth in claim 49, comprising word lines commonly connecting said gate electrodes in a word line direction, first common lines commonly connecting one of said two source and drain regions in a bit line direction, and second common lines commonly connecting the other of said two source and drain regions.

51. The nonvolatile semiconductor memory device as set forth in claim 50, wherein said first common lines include first sub-lines commonly connecting one of said source and drain regions in a bit line direction and first main lines commonly connecting the first sub-lines in a bit line direction;

said second common lines include

second sub-lines commonly connecting the other of said source and drain regions and

second main lines commonly connecting the second sub-lines; and

said plurality of memory transistors are connected in parallel between said first sub-lines and the second sub-lines.

52. The nonvolatile semiconductor memory device as set forth in claim 39, wherein a plurality of memory transistors each of which includes such channel forming region, said source and drain regions, said gate insulating film, and said gate electrode, are arranged in both a word line direction and a bit line direction;

said two source and drain regions comprises a semiconductor doped with the second conductivity type impurity, and

an element isolation layer is formed between one of said source and drain regions in one said memory transistor and the other of said source and drain regions in another said memory transistor adjacent to the former in the word line direction.

53. The nonvolatile semiconductor memory device as set forth in claim 39, wherein said charge storing means does not have conductivity as a plane as a whole facing said channel forming region at least when there is not dissipation of charges in the outside.

54. The nonvolatile semiconductor memory device as set forth in claim 53, wherein said gate insulating film comprises a bottom insulating film on said channel forming region, and a nitride film or an oxynitride film on said bottom insulating film.

55. The nonvolatile semiconductor memory devices as set forth in claim 53, wherein said gate insulating film comprises a bottom insulating film on said channel forming region, and mutually insulated small particle conductors formed on the bottom film and functioning as said charge storing means.

56. A method of operating a nonvolatile semiconductor memory device comprising:

a channel forming region comprised of a first conductivity type semiconductor, source and drain regions comprising of a second conductivity type semiconductor with said channel forming region in between, a gate insulating film provided on said channel forming region and including inside it a charge storing means dispersed in a plane facing said channel forming region and thickness direction, said gate insulating film comprising a first storage region retaining hot electrons injected from either said source region or said drain region, a second storage region retaining hot electrons injected from the other of said source and drain regions, and a third region between the first and the second region into which hot electrons are not injected, said third region comprising an insulating film of a single material, and a gate electrode provided on the gate insulating film;

said method comprising, in a write operation, a step of;

injecting hot electrons into said first storage region from one of said source and drain regions; and

injecting hot electrons from the other of said source and drain regions into said second storage region separated from the first storage region in the gate insulating film independently from the injection of hot electrons into said first storage region.

57. The method of operating a nonvolatile semiconductor memory device as set forth in claim 56, wherein;

said first and second storage regions are of stacked film structures comprising a plurality of films stacked on each other.

58. The method of operating a nonvolatile semiconductor memory device as set forth in claim 56, wherein

said first storage region retaining hot electrons from one of said source and drain regions is merged or partially merged in the gate insulating film with said second storage region retaining hot electrons from the other of said source and drain regions.

59. The method of operating a nonvolatile semiconductor memory device as set forth in claim 56, comprising, when writing data, a step of

applying a specified write voltage between said source and drain regions and said gate electrode.

60. The method of operating a nonvolatile semiconductor memory device as set forth in claim 56, wherein the gate length of a memory transistor including said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode is shorter than or equal to the gate length when said source and drain regions retaining hot electrons are merged or partially merged in the gate insulating film.

61. The method of operating a nonvolatile semiconductor memory device as set forth in claim 60, wherein:

a memory cell array comprised of a plurality of said memory transistors arranged in both a word line direction and bit line direction;

said gate insulating film in each said memory transistor each including said channel forming region, said two source and drain regions, said gate insulating film, and said gate electrode comprises a first storage region into which hot electrons are injected from one of said source and drain regions, a second storage region into which hot electrons are injected from the other of said source and drain regions, and a third region which is between said first and the second regions and into which hot electrons are not injected; and

said gate electrode in said memory transfer comprises a first gate electrode formed on said first storage region, a second gate electrode formed on said second storage region, and a third gate electrode formed on said third region,

said method comprising, when writing data to one region of said first and the second storage regions, a step of setting the gate electrode at the other of said first and second storage regions electrically floating, or applying a voltage of 0V or of an opposite polarity relative to said channel forming region to the gate electrode at the other of said first and the second storage regions.

62. The method of operating a nonvolatile semiconductor memory device as set forth in claim 60, said device having

a memory cell array comprised of a plurality of memory transistors each including said channel forming region, said two source and drain regions, said gate insulating film, and said gate electrode arranged in both a word line direction and bit line direction wherein said gate electrodes are commonly connected through the word lines for every certain number of memory transistors in a word line direction,

said method comprising, in a write operation, a step of

applying a voltage of 0V or of an opposite polarity relative to said channel forming region to the nonselected word lines to which a memory transistor to be operated is not connected.

63. The method of operating a nonvolatile semiconductor memory device as set forth in claim 56, wherein:

a memory cell array comprised of a plurality of memory transistors each including said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode arranged in both a word line direction and bit line direction;

one of said source and drain regions are commonly connected through first common lines for every certain number of memory transistors in a bit line direction; and

the other of said source and drain regions are commonly connected through second common lines,

said method comprising a step of;

applying a specific voltage to the first and/or the second common lines to which the memory transistor to be operated is connected; and

applying a voltage of 0V or of an polarity opposite to said specified voltage to the first and the second common lines to which the memory transistor to be operated is not connected.

64. The method of operating a nonvolatile semiconductor memory device as set forth in claim 63, wherein

in write operation of a memory cell array comprised of a plurality of said memory transistors each including said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode, arranged in both a word line direction and bit line direction wherein said gate electrodes are commonly connected through word lines for every certain number of memory transistors in a word line direction,

said method comprising in a write operation for all memory transistors connected to the same word line, step of:

applying a specified voltage to all of the source and drain regions corresponding to the first and the second storage regions into which hot electrons are injected;

setting the source and drain regions corresponding to the first and the second storage regions into which hot electrons injected in an electrically floating state;

applying a write voltage, which is equal to a predetermined difference with said specified voltage applied to said source and drain regions, on said same word line; and

writing all memory transistors connected to said same word line in parallel with one operation.

65. The method of operating a nonvolatile semiconductor memory device as set forth in claim 64, wherein:

said source and drain regions are comprised of a semiconductor doped with the second conductivity type impurity; and

said memory cell array is provided with an element isolation layer between one of said source and drain regions in one said memory transistor and the other of said source and drain regions in another said memory transistor adjacent to the former in the word line direction.

66. The method of operating a nonvolatile semiconductor memory device as set forth in claim 56, wherein:

in a read operation of said nonvolatile semiconductor memory device wherein

said gate insulating film in said memory transistor including said channel forming region, said source and drain regions, said gate insulating film, and said gate electrode

said gate insulating film comprises a first storage region into which hot electrons are injected from one of said source and drain regions, a second storage region into which hot electrons are injected from the other of said source and drain regions, and a third region which is between said first said the second regions and into which hot electrons are not injected; and

said gate electrode in said memory transistor comprises a first gate electrode formed on said first storage region, a second gate electrode formed on said second storage region, and a third gate electrode formed on said third region,

said method comprising in a read operation, steps of;

applying a specified read drain voltage between said source and drain regions so that the storage region to be read becomes the source;

applying a specified voltage to said third gate electrode; and

applying a specified read gate voltage of the same polarity as that applied to said third gate electrode to said first and/or the second gate electrodes.

67. The method of operating a nonvolatile semiconductor memory device as set forth in claim 56, comprising,

wherein erasing data, a step of extracting hot electrons which are injected from said source and drain regions and are stored in said charge storing means to the side of said source and drain regions by utilizing the direct tunneling effect or the FN tunneling effect.

68. The method of operating a nonvolatile semiconductor memory device as set forth in claim 56, comprising,

when erasing data, a step of extracting hot electrons which are injected from said source and drain regions and are separated and stored at the two sides of the charge storing means in the channel direction to the substrate side separately or simultaneously by utilizing the direct tunneling effect or the FN tunneling effect.

69. The method of operating a nonvolatile semiconductor memory device as set forth in claim 56, wherein

said first conductivity type is an n-type, and said second conductivity type is a p-type.

70. The method of operating a nonvolatile semiconductor memory device as set forth in claim 56, wherein

said charge storing means does not have conductivity as a plane as a whole facing said channel forming region at least when there is not dissipation of charges in the inside.

71. The method of operating a nonvolatile semiconductor memory device as set forth in claim 70, wherein said gate insulating film comprises:

a bottom insulating film on said channel forming region; and

a nitride film or an n oxynitride film on said bottom insulating film.

72. The method of operating a nonvolatile semiconductor memory device as set forth in claim 70, wherein said gate insulating film comprises:

a bottom insulating film on said channel forming region; and

mutually insulated small particle conductors formed on the bottom film and functioning as said charge storing means.