Cosine algorithm for relatively small angles

• US 6,434,582 B1
• Filed: 06/18/1999
• Issued: 08/13/2002
• Est. Priority Date: 06/18/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: MacDonald, James R., Choe, Gwangwoo
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/336,394
• Time in Patent Office: 1,152 Days
• Field of Search: 708/8, 708/276, 708/440
• US Class Current: 708/276
• CPC Class Codes: G06F 7/5446 using crossaddition algorithms, e.g. CORDIC

Abstract

A system and method for computing the cosine of an input value. The system comprises a logical processing unit and an addition unit. The logical processing unit comprises an input bus with a plurality of input lines for receiving an input angle value. The logical processing unit includes a first plurality of gates, preferably AND gates, coupled to the input bus. Each gate of the first plurality of gates couples to two or more of the input lines. The logical processing unit generates N output operands on N corresponding output buses. At least one of the output buses includes (a) at least one output line coupled to an output of one of the first plurality of gates, and (b) at least one output line coupled to one of the input lines of the input bus. The number N of output buses is greater than or equal to two. The addition unit couples to the N output buses of the logical processing unit, and is configured to perform an addition of the N binary operands provided on the N output buses. The addition unit generates a resultant number which represents the cosine of the input operand conveyed on the input bus. The input angle value is assumed to have a predetermined number of leading zeros. In general, output lines are coupled to (a) input lines, (b) outputs of gates, or (c) set equal to zero.

Claims

1. A cosine computation device comprising:

an input bus comprising a plurality of input lines, wherein the input bus is configured to receive an input value;

a logical processing unit coupled to the input bus, wherein the logical processing unit includes a first plurality of gates coupled to the input bus, wherein each gate of the first plurality of gates couples to two or more of the input lines, wherein the logical processing unit comprises N output buses, wherein at least one of said output buses includes (a) at least one output line which is coupled to an output of one of said first plurality of gates and (b) at least one output line which is coupled to one of the input lines of the input bus, wherein N is greater than or equal to two;

an addition unit coupled to the N output buses of the logical processing unit, wherein the addition unit is configured to perform an addition of N binary numbers corresponding to the N output buses and generate a resultant number which corresponds to a cosine of the input value.

2. The cosine computation device of claim 1 wherein each of said first plurality of gates is coupled to two of said input lines.

3. The cosine computation device of claim 1, wherein each of said first plurality of gates is an AND gate.

4. The cosine computation device of claim 1, wherein each of said output buses comprises (a) one or more first output lines each of which is driven by a corresponding gate of said first plurality of gates and (b) one or more second output lines each of which is set equal to a logical zero value.

5. The cosine computation device of claim 1 wherein the addition unit comprises:

a first carry save adder coupled to three output buses of said N output buses, wherein said first carry save adder is configured to add three binary numbers of said N binary numbers corresponding to said three output buses;

a second carry save adder coupled (a) to a fourth output bus of said N output buses and (b) to outputs of said first carry save adder, wherein said second carry save adder is configured to add a first number and a second number provided as outputs of the first carry save adder and a fourth number corresponding to the fourth output bus;

a carry propagate adder coupled to outputs of said second carry save adder, wherein the carry propagate adder is configured to generate the resultant number by adding two numbers corresponding to the outputs of said second carry save adder.

6. The cosine computation device of claim 1 wherein a first number of leading bits of said input value are guaranteed to be equal to zero, wherein said input lines receive bit values of said input value which are less significant than the leading bits which are guaranteed to be equal to zero.

7. The cosine computation device as recited in claim 1, further comprising a second plurality of gates, wherein each of said second plurality of gates includes (a) a first input coupled to an output of one of said first plurality of gates and (b) an output conductor coupled to an output line of one of said N output buses.

8. The cosine computation device as recited in claim 7, wherein said second plurality gates includes a first subset of gates, wherein each gate of said first subset includes a second input coupled to a second output of a second one said first plurality of gates.

9. The cosine computation device as recited in claim 7, wherein said second plurality of gates includes a second subset of gates, wherein each gates of said second subset includes another input coupled to one of the input lines of the input bus.

10. The cosine computation device of claim 7 wherein each of said second plurality of gates are AND gates.

11. A method for computing the cosine of an input value, the method comprising:

performing a plurality of AND operations on bits of the input value, wherein each of the AND operations operates on two or more bits of the input value;

generating N output operands, wherein at least one of the output operands includes (a) at least one output bit which is set equal to an input bit, and (b) at least one output bit which is set equal to the result of one of said AND operations, wherein N is greater than or equal to two;

adding the N output operands to generate a single resultant value which represents the cosine of the input value.

12. The method of claim 11, wherein each of said AND operations operates on exactly two bits of the input value.

13. The method of claim 11, wherein each of said output operands comprises (a) one or more first output bits each of which is set equal to the result of a corresponding AND operation, and (b) one or more second output bits each of which is set equal to a logical zero value.

14. The method of claim 11 wherein a first number of leading bits of said input value are guaranteed to be equal to zero, wherein said AND operations operate on bits of the input value which are less significant than the leading bits which are guaranteed to be equal to zero.