TCP/IP offload network interface device

• US 6,434,620 B1
• Filed: 08/27/1999
• Issued: 08/13/2002
• Est. Priority Date: 08/27/1998
• Status: Expired due to Term

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Higgen, David A., Philbrick, Clive M., Boucher, Laurence B., Craft, Peter K., Blightman, Stephen E. J., Starr, Daryl D.
• Primary Examiner(s): Maung, Zarni
• Application Number:
  US09/384,792
• Time in Patent Office: 1,082 Days
• Field of Search: 709/230, 709/250, 709/243, 709/228, 709/238
• US Class Current: 709/230
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: H04L 45/66 Layer 2 routing, e.g. in Ethernet based MAN's
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/193 at the transport layer, e.g. TCP related
• CPC Class Codes: H04L 47/36 by determining packet size, e.g. maximum transfer unit [MTU]
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload
• CPC Class Codes: H04L 49/9052 with buffers of different sizes
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9068 in the network interface card
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 61/00 Network arrangements, protocols or services for addressing or naming
• CPC Class Codes: H04L 61/10 : of different types
• CPC Class Codes: H04L 67/10 : in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 67/34 : involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 67/62 : Establishing a time schedule for servicing the requests
• CPC Class Codes: H04L 67/63 : Routing a service request depending on the request content or context
• CPC Class Codes: H04L 69/08 : Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/12 : Protocol engines
• CPC Class Codes: H04L 69/16 : Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 : Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/162 : involving adaptations of sockets based mechanisms secure socket layer H04L63/168
• CPC Class Codes: H04L 69/163 : In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/166 : IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/22 : Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 : Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 9/40 : Network security protocols

Abstract

An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors devoted to transmit, receive and utility processing, providing full duplex communication for four Fast Ethernet nodes.

Claims

1. A system, comprising:

a processor that performs slow-path network protocol processing, the slow-path network protocol processing being performed substantially in software; and

network protocol accelerator circuitry, the network protocol accelerator circuitry receiving a first network communication, the first network communication including a TCP header, the network protocol accelerator circuitry performing fast-path network processing on the first network communication such that the processor performs substantially no TCP protocol processing on the first network communication, the network protocol accelerator circuitry receiving a second network communication, the second network communication including a TCP header, the second network communication being associated with a connection, wherein the processor assumes control of the connection from the network protocol accelerator circuitry, the processor then performing slow-path network protocol processing on the second network communication.

2. The system of claim 1, wherein the connection is identified by a TCP source port in the second network communication, a TCP destination port in the second network communication, an IP source address in the second network communication, and an IP destination address in the second network communication.

3. The system of claim 1, wherein the second network communication is initially fast-path processed by the network protocol accelerator circuitry, and wherein the second network communication is subsequently slow-path processed by the processor.

4. The system of claim 1, wherein the first network communication includes a data payload, the network protocol accelerator circuitry receiving the first network communication, determining a final destination, and then placing the data payload into the final destination without the processor performing a substantial amount of fast-path processing on the first network communication.

5. A protocol accelerator integrated circuit that operates in conjunction with a processor, the processor executing a network protocol stack, the protocol accelerator integrated circuit receiving a first network communication from a network at substantially the same time that it outputs a second network communication to the network, the first network communication including a TCP header and an IP header, the second network communication including a TCP header and an IP header, the protocol accelerator integrated circuit comprising a pipeline of processors, the pipeline of processors including a receive processor and a transmit processor, the receive processor performing protocol processing on the first network communication such that the network protocol stack performs substantially no TCP protocol processing on the first network communication and such that the network protocol stack performs substantially no IP protocol processing on the first network communication, the transmit processor performing protocol processing on the second network communication such that the network protocol stack performs substantially no TCP protocol processing on the second network communication and such that the network protocol stack performs substantially no IP protocol processing on the second network communication.

6. The protocol accelerator integrated circuit of claim 5, wherein the protocol accelerator integrated circuit is disposed on a card, and wherein the processor is part of a host computer, the card being coupled to the host computer.