Optimized configurable scheme for demand based resource sharing of request queues in a cache controller

• US 6,434,673 B1
• Filed: 06/30/2000
• Issued: 08/13/2002
• Est. Priority Date: 06/30/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mosur, Lokpraveen B., Palanca, Salvador
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US09/607,794
• Time in Patent Office: 774 Days
• Field of Search: 711/100, 711/118, 711/133, 711/143, 711/151, 711/154, 711/158
• US Class Current: 711/133
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0859 with reload from main memory

Abstract

A method is provided that includes a step for setting a maximum number of concurrently allocated queue entries to service writeback evictions. The method also includes a step of setting a register bit based on cache requests. The method also includes a step for dynamically selecting, based on the register bit set, one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated in in any free entry based on priority. According to another embodiment of the invention, a computer system is provided that includes at least one computer processor. The computer processor provided has at least one cache memory and a cache controller. Further included is a register coupled to the computer processor. Also, a memory bus is provided that is coupled to the computer processor. A memory is included that is coupled to the memory bus. A controller for dynamically selecting between a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority is also included. The controller for dynamically selecting between one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority includes a register bit within the register that is capable of being set and cleared. The computer processor queries the register to determine if the register bit is either set and cleared.

Claims

1. A method comprising:

setting a maximum number of concurrently allocated queue entries in a cache controller to service writeback evictions;

setting a register bit based on cache requests; and

dynamically selecting, based on the register bit set, one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated in any free entry based on priority.

2. The method of claim 1, further comprising prioritizing writeback evictions and incoming core requests, wherein a higher priority is given to writeback evictions over incoming core requests.

3. The method of claim 1, wherein the cache controller has a single request queue and a corresponding single set of buffers, and a buffer in the corresponding single set of buffers is capable of servicing one of writeback evictions and core requests.

4. The method of claim 1, wherein the cache management scheme based on a maximum number of programmable writeback entries further comprises:

detecting a core request;

detecting a writeback request;

determining if a number of writeback entries is equal to the maximum number of allowable concurrent writeback evictions; and

performing one of stalling an issuance of a writeback request to a single cache queue if the number of writeback entries has reached the maximum number of

allowable writeback evictions and allocating an entry for a writeback and dispatching

an evict operation to the single cache queue if the number of writeback entries is less

than the maximum number of allowable writeback evictions.

5. The method of claim 1, wherein the cache management scheme based on a maximum number of programmable writeback entries further comprises:

detecting a core request and a writeback eviction request simultaneously;

detecting at least one available entry in a single cache controller queue;

determining if a number of writeback entries has reached the maximum number of concurrently allocated queue entries to service writeback evictions; and

stalling an issuance of a writeback eviction request to a single cache controller queue if the number of writeback entries has reached the maximum number of programmable writeback entries and accepting the core request due to available entries.

6. The method of claim 1, wherein the cache management scheme based on a maximum number of programmable writeback entries further comprises:

detecting a core request and a writeback eviction request simultaneously;

detecting at least two available entries in a single cache controller queue;

determining if a number of writeback entries has reached the maximum number of concurrently allocated queue entries to service writeback evictions; and

accepting both the core request and the writeback eviction request if the number of writeback entries is less than the maximum number of programmable writeback entries.

7. The method of claim 1, wherein the cache management scheme based on a maximum number of programmable writeback entries further comprises:

detecting a core request and a writeback eviction request simultaneously;

detecting only one available entry in a single cache controller queue;

determining if a number of writeback entries has reached the maximum number of concurrently allocated queue entries to service writeback evictions; and

giving higher priority to the writeback eviction request if the number of writeback entries is less than the maximum number of programmable writeback entries,

wherein the writeback eviction is accepted and the core request is stalled; and

re-issuing the stalled core request at a later time if an entry is available.

8. The method of claim 1, wherein the cache management scheme allowing both writeback entries and incoming core requests to be allocated in any free entry based on priority, further comprises:

detecting a core request;

detecting a writeback request;

prioritizing the writeback entry and an incoming core request;

determining if any entries are available;

allocating a first entry for a writeback eviction;

allocating an entry for the incoming core request if a second entry is available; and

redispatching the incoming core request if no additional entries are available.

9. The method of claim 1, wherein both the cache management scheme allowing both writeback entries and incoming core requests to be allocated in any free entry based on priority and the cache management scheme based on a maximum number of programmable writeback entries, further comprise:

detecting a core request;

detecting a writeback request;

determining if no entries are available in a single cache controller;

stalling both the core request and the writeback request if no entries are available in the single cache controller.

10. The method of claim 1, wherein both the cache management scheme allowing both writeback entries and incoming core requests to be allocated in any free entry based on priority and the cache management scheme based on a maximum number of programmable writeback entries, wherein at least one entry is reserved in a single cache controller queue for one of servicing writeback evictions and deallocating entries servicing core requests if a cache miss occurs.

11. A method comprising

setting a maximum number of allowable writeback evictions;

allocating a plurality of entries in a cache for a plurality of writeback evictions and a plurality of core requests;

detecting a core request;

detecting a writeback request;

determining if a number of writeback entries is equal to the maximum number of allowable writeback evictions;

stalling an issuance of a writeback request to a single cache queue if the number of writeback entries is equal to the maximum number of allowable writeback evictions;

allocating an entry for a writeback and dispatching an evict operation to the single cache queue if the number of writeback entries is less than the maximum number of allowable writeback evictions; and

controlling a queue in a cache controller.

12. The method of claim 11, further comprising prioritizing writeback evictions and incoming core requests, wherein a higher priority is given to writeback evictions over incoming core requests.

13. The method of claim 11, wherein the cache controller has a single request queue and a corresponding single set of buffers, and a buffer in the corresponding single set of buffers is capable of servicing one of writeback evictions and core requests.

14. A computer-readable medium having a sequence of instructions stored thereon, the sequence of instructions, when executed by a processor, causes the processor to perform operations comprising:

setting a maximum number of concurrently allocated queue entries in a cache controller to service writeback evictions;

setting a register bit based on cache requests; and

dynamically selecting, based on the register bit set, one of a cache management scheme based on a maximum number of programmable writeback entries and a cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority.

15. The computer-readable medium of claim 14, further comprising a sequence of instructions, when executed by a processor, cause the processor to perform prioritizing of writeback evictions and incoming core requests, wherein a higher priority is given to writeback evictions over incoming core requests.

16. The computer-readable medium of claim 14, wherein the cache controller has a single request queue and a corresponding single set of buffers, and a buffer in the corresponding single set of buffers is capable of servicing one of writeback evictions and core requests.

17. The computer-readable medium of claim 14, wherein the cache management scheme based on a maximum number of programmable writeback entries further comprises:

detecting a core request;

detecting a writeback request;

determining if a number of writeback entries is equal to the maximum number of allowable concurrent writeback evictions;

performing one of stalling an issuance of a writeback request to a single cache queue if the number of writeback entries has reached the maximum number of allowable writeback evictions, and allocating an entry for a writeback and dispatching an evict operation to the single cache queue if the number of writeback entries is less than the maximum number of allowable writeback evictions.

18. The computer-readable medium of claim 14, wherein the cache management scheme based on a maximum number of programmable writeback entries further comprises:

detecting a core request and a writeback eviction request simultaneously;

detecting at least one available entry in a single cache controller queue;

determining if a number of writeback entries has reached the maximum number of concurrently allocated queue entries to service writeback evictions; and

stalling an issuance of a writeback eviction request to a single cache controller queue if the number of writeback entries has reached the maximum number of programmable writeback entries and accepting the core request due to available entries.

19. The computer-readable medium of claim 14, wherein the cache management scheme based on a maximum number of programmable writeback entries further comprises:

detecting a core request and a writeback eviction request simultaneously;

detecting at least two available entries in a single cache controller queue;

determining if a number of writeback entries has reached the maximum number of concurrently allocated queue entries to service writeback evictions; and

accepting both the core request and the writeback eviction request if the number of writeback entries is less than the maximum number of programmable writeback entries.

20. The computer-readable medium of claim 14, wherein the cache management scheme based on a maximum number of programmable writeback entries further comprises:

detecting a core request and a writeback eviction request simultaneously;

detecting only one available entry in a single cache controller queue;

determining if a number of writeback entries has reached the maximum number of concurrently allocated queue entries to service writeback evictions; and

giving higher priority to the writeback eviction request if the number of writeback entries is less than the maximum number of programmable writeback entries,

wherein the writeback eviction is accepted and the core request is stalled; and

re-issuing the stalled core request at a later time if an entry is available.

21. The computer-readable medium of claim 14, wherein the cache management scheme allowing both writeback entries and incoming core requests to be allocated based on priority, further comprises:

detecting a core request;

detecting a writeback request;

prioritizing the writeback entry and an incoming core request;

determining if any entries are available;

allocating a first entry for a writeback eviction;

allocating an entry for the incoming core request if a second entry is available; and

redispatching the incoming core request if no additional entries are available.

22. The computer-readable medium of claim 14, wherein both the cache management scheme allowing both writeback entries and incoming core requests to be allocated in any free entry based on priority and the cache management scheme based on a maximum number of programmable writeback entries, further comprise:

detecting a core request;

detecting a writeback request;

determining if no entries are available in a single cache controller;

stalling both the core request and the writeback request if no entries are available in the single cache controller.

23. The computer-readable medium of claim 14, wherein both the cache management scheme allowing both writeback entries and incoming core requests to be allocated in any free entry based on priority, and the cache management scheme based on a maximum number of programmable writeback entries, wherein at least one entry is reserved in a single cache controller queue for one of servicing writeback evictions and deallocating entries servicing core requests if a cache miss occurs.

24. A computer-readable medium having a sequence of instructions stored thereon, the sequence of instructions, when executed by a processor, causes the processor to perform operations comprising:

setting a maximum number of concurrently allocated queue entries to service writeback evictions;

detecting a core request;

detecting a writeback request;

allocating a plurality of entries in a cache for a plurality of writeback evictions and a plurality of core requests;

determining if a number of writeback entries is equal to the maximum number of allowable writeback evictions;

stalling an issuance of a writeback request to a single cache queue if the number of writeback entries is equal to the maximum number of allowable writeback evictions; and

allocating an entry for a writeback and dispatching an evict operation to the single cache queue if the number of writeback entries is less than the maximum number of allowable writeback evictions.

25. The computer-readable medium of claim 24, further comprising a sequence of instructions, when executed by a processor, cause the processor to perform prioritizing of writeback evictions and incoming core requests, wherein a higher priority is given to writeback evictions over incoming core requests.

26. The computer-readable medium of claim 24, wherein the cache controller has a single request queue and a corresponding single set of buffers;

and

a buffer in the corresponding single set of buffers is capable of servicing one of writeback evictions and core requests.