Encryption processor with shared memory interconnect

• US 6,434,699 B1
• Filed: 06/01/2000
• Issued: 08/13/2002
• Est. Priority Date: 02/27/1998
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Jones, David E., OʼConnell, Cormac M.
• Primary Examiner(s): Peeso, Thomas R.
• Application Number:
  US09/584,930
• Time in Patent Office: 803 Days
• Field of Search: 713/168, 713/200, 713/201, 380/255, 380/28
• US Class Current: 713/168
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 7/49931 Modulo N reduction of final result
• CPC Class Codes: G06F 7/5052 using carry completion detection, either over all stages or at sample stages only
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
• CPC Class Codes: G06F 7/72 using residue arithmetic
• CPC Class Codes: G06F 7/722 Modular multiplication G06F7/724, G06F7/727, G06F7/728 take precedence
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/14 using a plurality of keys or algorithms

Abstract

An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.

Claims

1. A programmable encryption device to process a plurality of secret key and public key encryption algorithms comprising, on a single chip:

an array of processing elements which process successive rounds of an encryption algorithm in a processing element pipeline;

a public key core processor which performs a public key encryption algorithm;

global memory for global communication among the processing elements and for data transfer to and from the public key core processor; and

a control CPU which controls operations of the encryption device.

2. An encryption device as claimed in claim 1 further comprising a global data bus connecting the array of processing elements, the global memory and the control CPU.

3. An encryption device as claimed in claim 1 further comprising I/O communication logic through which the encryption device is programmed from a host CPU.

4. An encryption device as claimed in claim 1 further comprising:

an input stage which receives a data stream to be encrypted and converts the data stream to block aligned data suitable for processing in the array of processing elements; and

an output stage which converts encrypted data to a data stream to be output from the encryption device.