Two moment RC delay metric for performance optimization

• US 6,434,729 B1
• Filed: 04/04/2000
• Issued: 08/13/2002
• Est. Priority Date: 04/04/2000
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Devgan, Anirudh, Alpert, Charles Jay, Kashyap, Chandramouli V.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/542,442
• Time in Patent Office: 861 Days
• Field of Search: 716/1-21, 703/2, 703/14-17, 703/19
• US Class Current: 716/113
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

An efficient method for optimizing RC circuit design to reduce delay. The method comprises: calculating a first moment and a second moment of impulse response for an RC circuit; (2) computing a delay value for each node of the RC circuit utilizing the first and second moments by multiplying the natural logarithm of 2 with a division of the squared power of the first impulse moment by the square root of the second impulse moment; and (3) analyzing each node to determine if the delay at that node is at a desired optimization condition for optimizing the circuit response.

Claims

1. An efficient method for estimating delays at nodes in an RC circuit, said method comprising the steps of:

calculating a first impulse moment and a second impulse moment of an RC circuit;

computing a circuit delay value at each node of said RC circuit utilizing said first and second impulse moments by multiplying a natural logarithm of 2 with a division of a squared power of the first impulse moment by a square root of the second impulse moment; and

determining, based on said circuit delay value, whether said RC circuit meets a desired optimization condition.

2. The method of claim 1, wherein said calculating step includes the step of determining a value of said R and said C at said each node.

3. The method of claim 1, wherein said desired optimization condition in said determining step is a maximum delay value for said each node, and said determining step further comprises the step of comparing said circuit delay value with said maximum delay value, wherein said RC circuit meets said desired optimization condition when said circuit delay value is less than said maximum delay value.

4. The method of claim 1, further comprising the step of adjusting circuit elements of said RC circuit to cause a later calculated circuit delay value to be less than said maximum delay value, when said circuit delay value does not meet said desired optimization condition.

5. A computer program product for estimating delays at nodes in an RC circuit, said program product comprising:

a computer readable medium; and

program instructions on said computer readable medium for;

calculating a first impulse moment and a second impulse moment of an RC circuit;

computing a circuit delay value at each node of said RC circuit utilizing said first and second impulse moments by multiplying a natural logarithm of 2 with a division of a squared power of the first impulse moment by a square root of the second impulse moment; and

determining, based on said circuit delay value, whether said RC circuit meets a desired optimization condition.

6. The computer program product of claim 5, wherein said program instructions for said computing step includes program instructions for determining a value of said R and said C at said each node.

7. The computer program product of claim 5, wherein said desired optimization condition in said program instructions for said determining step is a maximum delay value for said each node, and said program instructions for said determining step further comprises program instructions for comparing said circuit delay value with said maximum delay value, wherein said RC circuit meets said desired optimization condition when said circuit delay value is less than said maximum delay value.

8. The computer program product of claim 5, further comprising program instructions for adjusting circuit elements of said RC circuit to cause a later calculated circuit delay value to be less than said maximum delay value, when said circuit delay value does not meet said desired optimization condition.

9. A data processing system for estimating delays at nodes in an RC circuit, said data processing system comprising:

a processor;

an input and output mechanism coupled to said processor; and

program code stored within a medium accessible by said processor for;

calculating a first impulse moment and a second impulse moment of an RC circuit,

computing a circuit delay value at each node of said RC circuit utilizing said first and second impulse moments by multiplying a natural logarithm of 2 with a division of a squared power of the first impulse moment by a square root of the second impulse moment; and

outputting said circuit delay value utilizing output mechanism.

10. The data processing system of claim 9, further comprising program code for:

accepting a user inputted desired optimization condition via said input mechanism; and

determining, based on said circuit delay value, whether said RC circuit meets said desired optimization condition.

11. The data processing system of claim 10, wherein said desired optimization condition in said determining step is a maximum delay value for said each node, and said program code for said determining step further comprises program code for comparing said circuit delay value with said maximum delay value, wherein said RC circuit meets said desired optimization condition when said circuit delay value is less than said maximum delay value.

12. The data processing system of claim 10, wherein said out mechanism comprises a graphical user interface, which identifies said each node and a corresponding delay value at said each node, and whereby circuit topology is visually manipulated.

13. The data processing system of claim 9, wherein said program code for said calculating step includes the program code for determining a value of said R and said C at said each node.

14. The data processing system of claim 9, further comprising program code for accepting adjustments to circuit elements of said RC circuit to cause a later calculated circuit delay value to be less than said maximum delay value, when said circuit delay value does not meet said desired optimization condition.

15. The data processing system of claim 9, further comprising program code for generating RC circuit topology based on values of circuit components and circuit parameters entered at said input mechanism.