Data pipeline system and data encoding method

• US 6,435,737 B1
• Filed: 06/07/1995
• Issued: 08/20/2002
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Chartoleaux KG LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Wise, Adrian Philip, Robbins, William Philip, Sotheran, Martin William
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/482,296
• Time in Patent Office: 2,631 Days
• Field of Search: 395/375, 395/800, 395/800.28, 395/376
• US Class Current: 712/200
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Claims

1. In a system having a data stream including run level code, the improvement characterized by:

an interfacing token for control and/or data functions in said data stream, wherein said token comprises a plurality of data words, each said word including an extension indicator which indicates a presence or an absence of additional words in said token, a length of said token being determined by said extension indicators, whereby the length of said token can be unlimited,

inverse modeler means active upon said data stream and responsive to said token for expanding out said run level code to a run of zero data followed by a level, whereby each token is expressed with a specified number of values.

2. A system as recited in claim 1, wherein said token is a DATA token.

3. A system as recited in claim 1, wherein said inverse modeler means blocks tokens which lack said specified number of values.

4. A system as recited in any of claims 1, 2 and 3 wherein said specified number of values is 64 coefficients.

5. The system according to claim 1, further comprising an inverse quantizer circuit coupled to said inverse modeler means by a two-wire interface, wherein said two-wire interface comprises:

a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.

6. In a system having a data stream including run level code, the improvement characterized by:

inverse modeler means active upon said data stream and responsive to a token for expanding out said run level code to a run of zero data followed by a level, whereby said token is expressed with a specified number of values, an output of said inverse modeler means being communicated via a first two-wire interface, said two-wire interface comprising a sender, a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready; and

an interfacing token for control and/or data functions in said data stream, wherein said token comprises a plurality of data words, each said word including an extension indicator which indicates a presence or an absence of additional words in said token, a length of said token being determined by said extension indicators, whereby the length of said token can be unlimited.

7. The system according to claim 6, wherein said inverse modeler receives said data stream via a second two-wire interface.