Photolithographic apparatus composed of coater/developer and a plurality of steppers in parallel connected thereto

• US 6,436,609 B1
• Filed: 05/04/2000
• Issued: 08/20/2002
• Est. Priority Date: 08/20/1997
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Tae-sin
• Primary Examiner(s): Huff, Mark F.
• Assistant Examiner(s): BARRECA, NICOLE M
• Application Number:
  US09/565,629
• Time in Patent Office: 838 Days
• Field of Search: 430/311, 430/313, 430/328, 430/329
• US Class Current: 430/313
• CPC Class Codes: G03F 7/70991 Connection with other apparatus, e.g. multiple exposure stations, particular arrangement of exposure apparatus and pre-exposure and/or post-exposure apparatus; Shared apparatus, e.g. having shared radiation source, shared mask or workpiece stage, shared base-plate; Utilities, e.g. cable, pipe or wireless arrangements for data, power, fluids or vacuum
• CPC Class Codes: Y10S 414/135 Associated with semiconductor wafer handling

Abstract

A photolithographic apparatus for rapidly processing semiconductor wafers. In the photolithographic apparatus, a plurality of steppers are in parallel connected to one coater/developer. The steppers are in parallel connected to one coater/developers, where the steppers process the semiconductor wafer at a low speed and the coater/developers process the semiconductor wafer at a high speed, to thereby remove a bottleneck phenomenon. Therefore, the photolithographic apparatus according to the present invention may rapidly perform a photolithography process.

Claims

1. A photolithographic process for manufacturing semiconductor devices, comprising:

providing a single coater for coating a photoresist film on semiconductor wafers, a single developer and a plurality of steppers, the plurality of steppers parallel-connected to said single coater and said single developer;

coating a plurality of uncoated semiconductor wafers in said single coater;

transmitting said plurality of coated semiconductor wafers to said plurality of steppers;

parallel-exposing said plurality of coated semiconductor wafers in at least two of said plurality of steppers parallel-connected to said single coater and said single developer to a photolithographic pattern; and

developing said predetermined photolithographic pattern in said single developer thereby increasing the speed of said photolithographic processing of the semiconductor wafers.

2. The photolithographic process of claim 1, wherein the number of steppers is between two and five inclusive.

3. The photolithographic process of claim 1, which further includes providing a loader/unloader and receiving and transmitting semiconductor wafers employing said loader/unloader after said photolithography process is completed.

4. The photolithographic process of claim 1, which further includes the step of treating said semiconductor wafers to increase adhesion of the semiconductor wafers to a photoresist film.

5. The photolithographic process of claim 1, which further includes providing a plurality of spin coaters in addition to the single coater of claim 1 and coating the photoresist film on the semiconductor wafers in said plurality of spin coaters.

6. The photolithographic process of claim 1, which further includes the step of soft-baking or hard-baking the photoresist film.

7. The photolithographic process of claim 1, which further includes the step of edge exposing the coated semiconductor wafers which have been exposed in the steppers.

8. A photolithographic process for manufacturing semiconductor devices, comprising:

coating with a photoresist material a plurality of uncoated semiconductor wafers in a single coater;

transmitting said plurality of coated semiconductor wafers to a plurality of steppers;

exposing said plurality of coated semiconductor wafers to a photolithographic pattern in said plurality of steppers adapted to process the wafers at substantially the same time;

introducing said coated semiconductor wafers having a photolithographic pattern printed therein to a single developer; and

developing said photolithographic pattern in said coated semiconductor wafers in said single developer thereby increasing the speed of said photolithographic processing of the semiconductor wafers.

9. The photolithographic process of claim 8, wherein the number of steppers is two through five.

10. The photolithographic process of claim 8, which further includes the step of soft-baking or hard-baking the photoresist film.

11. The photolithographic process of claim 8, which further includes the step of edge exposing the coated semiconductor wafers which have been exposed in the steppers.