Semiconductor integrated circuit device

• US 6,436,741 B2
• Filed: 04/02/2001
• Issued: 08/20/2002
• Est. Priority Date: 03/10/2000
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Uchiyama, Kunio, Sato, Masayuki
• Primary Examiner(s): Ho, Hoai V.
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/822,429
• Publication Number:
  US 20010021558A1
• Time in Patent Office: 505 Days
• Field of Search: 438/149, 438/199, 438/200, 438/201, 438/239, 438/286, 438/290, 365/154, 365/189, 365/200, 365/201, 365/185, 365/159
• US Class Current: 438/149
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/1206 Location of test circuitry on chip or wafer
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Abstract

A logic test having less over-head for testing a logic circuit in a chip is implemented by constituting a test circuit in the chip without introducing a novel device process of FPGA. A memory of a self-configuration type is provided in the chip and a test circuit is constituted in the memory of a self-configuration type or an ordinary memory through a tester HDL, thereby testing other memories and logic circuits in the chip. The test circuit is reconstituted such that the memory used in the structure of the test circuit can be operated as an ordinary memory.

Claims

1. A method of manufacturing a semiconductor integrated circuit device comprising a logic circuit, and a plurality of first storage circuits and a second storage circuit acting as a storage circuit capable of constituting an optional logic for the semiconductor integrated circuit device;

said second storage circuit including a memory array capable of reading and writing data from a memory cell specified by an address signal;

an address decoder to decode the address signal and to generate a signal to select a memory cell in the memory array;

a feedback path to feed back data read from the memory array to an input side of the address decoder;

a switch matrix capable of switching an input address signal or a signal fed back through the feedback path so as to supply the switched signal to the address decoder; and

a memory to store control information of each switch in the switch matrix;

comprising the steps of;

constituting, on said second storage circuit, a test circuit to check said first storage circuits and/or said logic circuit;

testing said first storage circuits and/or the logic circuit by the test circuit; and

reconstituting said second storage circuit after the test for said first storage circuits and/or the logic circuit is completed.

2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein, at the testing step to be carried out by the test circuit, a result of the test obtained by the test circuit is stored in one of said first storage circuits.

3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising a redundancy processing step of replacing a fail memory cell in said memory array detected at the test step with a spare memory cell after completing the test of one of the first storage circuits in a case in which the first storage circuit includes a redundant circuit for replacing the fail memory cell with the spare memory cell.

4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein at the step of constituting a test circuit on said second storage circuit, design data having a function level described in a hardware description language are decoded by control means, and a signal for determining a logical structure of the second storage circuit is given from the control means to the second storage circuit so that a logic circuit having a desirable logic function is constituted.