Method for fabricating a thin film transistor with silicon oxynitride film and silicon nitride channel passivation film for preventing a back channel effect
First Claim
1. A method for fabricating a thin film transistor comprising the steps of:
- sequentially forming a gate insulating film, a silicon layer, a silicon oxynitride film and a channel passivation film in this order on an insulating substrate and a gate electrode formed on said insulating substrate wherein said silicon oxynitride film is formed by a chemical vapor deposition method using a mixed gas containing SiH4, N2 and NO2, and wherein an electric power and a time in said chemical vapor deposition method are controlled to generate a plasma of said mixed gas for forming said silicon oxynitride film of a thickness equal to or less than 50 Å
on said amorphous silicon layer;
depositing a resist layer on said channel passivation film and forming a pattern of resist mask at a position above said gate electrode;
etching portions of said channel passivation film and said silicon oxynitride film which are not covered by said resist mask;
removing said resist mask;
depositing a low resistive film on an entire surface of the structure;
forming a source electrode and a drain electrode on said low resistive film at positions on both sides of said remaining channel passivation film; and
removing a portion of said low resistive film which is placed on a back channel region between said source electrode and said drain electrode.
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Abstract
The present invention provides a thin film transistor (TFT) and a fabrication method thereof which suppresses the back channel effects in which a leakage current flows between a source electrode and a drain electrode at times during a turn off state of the TFT. A thin silicon oxynitride film 90 having a thickness preferably equal to or less than 50 Å is formed between an amorphous silicon layer 40 and a channel passivation film 50 (a silicon nitride film) above a back channel region 100 between a source electrode and a drain electrode of an inverted staggered type TFT to cause Si—O bonds to exist in an upper interface of the amorphous silicon layer. The Si—O bonds increase the Density of States in the back channel region and has an effect for suppressing the leakage current through the back channel region 100 at times during the turn off of the TFT.
10 Citations
11 Claims
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1. A method for fabricating a thin film transistor comprising the steps of:
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sequentially forming a gate insulating film, a silicon layer, a silicon oxynitride film and a channel passivation film in this order on an insulating substrate and a gate electrode formed on said insulating substrate wherein said silicon oxynitride film is formed by a chemical vapor deposition method using a mixed gas containing SiH4, N2 and NO2, and wherein an electric power and a time in said chemical vapor deposition method are controlled to generate a plasma of said mixed gas for forming said silicon oxynitride film of a thickness equal to or less than 50 Å
on said amorphous silicon layer;
depositing a resist layer on said channel passivation film and forming a pattern of resist mask at a position above said gate electrode;
etching portions of said channel passivation film and said silicon oxynitride film which are not covered by said resist mask;
removing said resist mask;
depositing a low resistive film on an entire surface of the structure;
forming a source electrode and a drain electrode on said low resistive film at positions on both sides of said remaining channel passivation film; and
removing a portion of said low resistive film which is placed on a back channel region between said source electrode and said drain electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification
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- Resources
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Current AssigneeLenovo Singapore Pte Limited (Lenovo Group Ltd.)
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Original AssigneeInternational Business Machines Corporation
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InventorsMiyamoto, Takashi, Tsujimura, Takatoshi
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Primary Examiner(s)Fahmy, Wael
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Assistant Examiner(s)LEE, HSIEN MING
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Application NumberUS09/871,363Publication NumberTime in Patent Office446 DaysField of Search438/30, 438/149, 438/156, 438/158, 438/161, 257/59, 257/241, 257/291US Class Current438/149CPC Class CodesH01L 29/66765 Lateral single gate single ...H01L 29/78609 for preventing leakage curr...H01L 29/78669 with inverted-type structur...
