Method of copper barrier layer formation

• US 6,436,825 B1
• Filed: 04/03/2000
• Issued: 08/20/2002
• Est. Priority Date: 04/03/2000
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shue, Shau-Lin
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, DUNG ANH
• Application Number:
  US09/541,481
• Time in Patent Office: 869 Days
• Field of Search: 438/687, 438/637, 438/638, 438/639, 438/640, 438/653, 438/672, 438/674, 438/675, 257/751, 257/752
• US Class Current: 438/687
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76864 Thermal treatment

Abstract

A process in the fabrication of integrated circuits has been developed for copper diffusion barrier layer. This invention teaches a method of barrier formation by the deposition by physical vapor deposition (PVD) sputtering (reactive sputtering for nitride compounds) or chemical vapor deposition (CVD) of a copper metal diffusion barrier layer, which consists of the following materials: TaN, Ta, TiN, or WN. Next in the process, is the plasma silation and silicon doping of the barrier layer material followed by high temperature thermal annealing. Scanning electron microscope (SEM) analysis of the silated barrier materials show amorphous films with clusters of silicide material with low silicon concentration and high film density (>99%). Low diffusion properties (amorphous films lack grains for fast grain boundary diffusion) and good chemical vapor deposited (CVD) copper seed layer adhesion, are found with the both TiSiN and TaSiN barrier layers made by this method. The current invention applies to lining both a single and dual damascene structure to form copper metal barrier layers and adhesive copper seed layer for interconnects and vias prior to electrochemical deposition (ECD) of copper.

Claims

1. A method of copper diffusion barrier formation comprising:

providing a dielectric layer having an opening to copper metal interconnect wiring;

depositing a diffusion barrier layer over the dielectric layer covering and lining the opening;

doping with silicon the surface of the diffusion barrier layer by a silane plasma treatment to form silated silicon doped compounds on the surface of the diffusion barrier layer;

annealing thermally at high temperature the surface of the silicon doped diffusion barrier layer to drive in the silated silicon doped compounds into the diffusion barrier layer and to form a highly dense, amorphous silicon doped diffusion barrier layer.

2. The method of claim 1, further comprising a semiconductor single crystal silicon substrate.

3. The method of claim 1, wherein the dielectric layer is selected from the group consisting of silicon dioxide or silicon oxide.

4. The method of claim 1, wherein the opening is lined with a copper diffusion barrier layer deposited by sputtering physical vapor deposition technique, reactive sputter for nitride, or chemical vapor deposition and the barrier layer material is selected from the group consisting of TaN, Ta, TiN, and WN, with film thickness from 50 to 700 Angstroms.

5. The method of claim 1, wherein the opening is lined with said copper diffusion barrier layer and plasma treated with silane to dope the surface of said diffusion barrier layer with silicon by a plasma process, with power from 300 to 600 Watts and time of about 5 to 240 seconds.

6. The method of claim 1, wherein the copper diffusion barrier layer is thermally annealed at high temperature with silane gas, for the TiSiN silicon doped barrier layer annealing at 600°

C. producing an amorphous highly dense film, and for the TaSiN silicon doped barrier layer annealing at 900°

C. producing an amorphous highly dense film.

7. The method of claim 1, further comprising the opening is lined with an adhesive copper seed layer on said copper diffusion barrier layer, the copper seed layer deposited by chemical vapor deposition or physical vapor deposition, with the seed layer type material being conducting copper metal in the film thickness range from approximately 50 to 300 Angstroms.

8. The method of claim 1, further comprising a conducting material layers for conducting interconnect lines are formed by electrochemical deposition of copper metal deposited in the opening without seams or voids upon a seed layer and said copper diffusion barrier layer.

9. The method of claim 1, further comprising a level of conducting copper metal is planarized by removing excess conducting material, by a method selected from the group consisting of planarization by chemical mechanical polish, milling, ion milling, and/or etching, leaving only the copper that lies in the opening to form single inlaid structures that include conducting interconnect lines and contact vias.

10. The method of claim 1, further comprising a method whereby multilevel conducting structures are fabricated by repeating the process described herein.

11. A method for fabricating a copper diffusion barrier layer comprising:

providing a dielectric layer having an opening to copper metal interconnect wiring;

depositing a diffusion barrier layer over the dielectric layer covering and lining the opening;

doping with silicon the surface of the diffusion barrier layer by a silane plasma treatment to form silated silicon doped compounds on the surface of the diffusion barrier layer;

annealing thermally at high temperature the surface of the silicon doped diffusion barrier layer to drive in the silated silicon doped compounds into the diffusion barrier layer and to form a highly dense, amorphous silicon doped diffusion barrier layer;

depositing a copper seed layer over the silicon doped diffusion barrier layer;

thus, forming robust defect-free copper diffusion barrier layer and copper seed layer for subsequent electrochemical deposition of plated copper upon the copper seed layer and chem-mech polishing back of excess copper to form inlaid copper interconnects.

12. The method of claim 11, further comprising a semiconductor single crystal silicon substrate.

13. The method of claim 11, wherein the dielectric layer is selected from the group consisting of silicon dioxide or silicon oxide.

14. The method of claim 11, wherein the opening is lined with a copper diffusion barrier layer deposited by sputtering physical vapor deposition technique, reactive sputter for nitride, or chemical vapor deposition and the barrier layer material is selected from the group consisting of TaN, Ta, TiN, and WN, with film thickness from 50 to 700 Angstroms.

15. The method of claim 11, wherein the opening is lined with said copper diffusion barrier layer and plasma treated with silane to dope the surface of said diffusion barrier layer with silicon by a plasma process, with power from 300 to 600 Watts and time of about 5 to 240 seconds.

16. The method of claim 11, wherein the copper diffusion barrier layer is thermally annealed at high temperature with silane gas, for the TiSiN silicon doped barrier layer annealing at 600°

C. producing an amorphous highly dense film, and for the TaSiN silicon doped barrier layer annealing at 900°

C. producing an amorphous highly dense film.

17. The method of claim 11, further comprising the opening is lined with an adhesive copper seed layer on said copper diffusion barrier layer, the copper seed layer deposited by chemical vapor deposition or physical vapor deposition, with the seed layer type material being conducting copper metal in the film thickness range from approximately 50 to 300 Angstroms.

18. The method of claim 11, further comprising a conducting material layers for conducting interconnect lines are formed by electrochemical deposition of copper metal deposited in the opening without seams or voids upon a seed layer and said copper diffusion barrier layer.

19. The method of claim 11, further comprising a level of conducting copper metal is planarized by removing excess conducting material, by a method selected from the group consisting of planarization by chemical mechanical polish, milling, ion milling, and/or etching, leaving only the copper that lies in the opening to form single inlaid structures that include conducting interconnect lines and contact vias.

20. The method of claim 11, further comprising a method whereby multilevel conducting structures are fabricated by repeating the process described herein.

21. A method for fabricating MOSFET and CMOS devices on a silicon semiconductor substrate with damascene structures using electrochemical deposition of copper and chemical vapor deposition of copper seed layer on a silicon doped diffusion barrier layer comprising:

providing a semiconductor substrate having an insulating layer deposited upon said substrate;

providing a level of copper metal interconnect wiring patterned within an insulating layer over said insulating layer;

providing a dielectric layer having an opening to the copper metal interconnect wiring;

depositing a diffusion barrier layer over the dielectric layer covering and lining the opening, with the diffusion barrier layer material selected from the group consisting of TaN, Ta, TiN and WN;

doping with silicon the surface of the diffusion barrier layer by a silane plasma treatment to form silated silicon doped compounds on the surface of the diffusion barrier layer;

annealing thermally at high temperature the surface of the silicon doped diffusion barrier layer to drive in the silated silicon doped compounds into the diffusion barrier layer and to form a highly dense, amorphous silicon doped diffusion barrier layer;

depositing a copper seed layer over the silicon doped diffusion barrier layer;

depositing by electrochemical deposition copper conducting material over the copper seed layer and removing the excess material layers by chemical mechanical polish to form conducting copper interconnects and contact vias, which are inlaid structures.

22. The method of claim 21, further comprising a semiconductor single crystal silicon substrate.

23. The method of claim 21, wherein the dielectric layer is selected from the group consisting of silicon dioxide or silicon oxide.

24. The method of claim 21, wherein the opening is lined with a copper diffusion barrier layer deposited by sputtering physical vapor deposition technique, reactive sputter for nitride, or chemical vapor deposition and the barrier layer material is selected from the group consisting of TaN, Ta, TiN, and WN, with film thickness from 50 to 700 Angstroms.

25. The method of claim 21, wherein the opening is lined with said copper diffusion barrier layer and plasma treated with silane to dope the surface of said diffusion barrier layer with silicon by a plasma process, with power from 300 to 600 Watts and time of about 5 to 240 seconds.

26. The method of claim 21, wherein the copper diffusion barrier layer is thermally annealed at high temperature with silane gas, for the TiSiN silicon doped barrier layer annealing at 600°

C. producing an amorphous highly dense film, and for the TaSiN silicon doped barrier layer annealing at 900°

C. producing an amorphous highly dense film.

27. The method of claim 21, further comprising the opening is lined with an adhesive copper seed layer on said copper diffusion barrier layer, the copper seed layer deposited by chemical vapor deposition or physical vapor deposition, with the seed layer type material being conducting copper metal in the film thickness range from approximately 50 to 300 Angstroms.

28. The method of claim 21, further comprising a conducting material layers for conducting interconnect lines are formed by electrochemical deposition of copper metal deposited in the opening without seams or voids upon a seed layer and said copper diffusion barrier layer.

29. The method of claim 21, further comprising a level of conducting copper metal is planarized by removing excess conducting material, by a method selected from the group consisting of planarization by chemical mechanical polish, milling, ion milling, and/or etching, leaving only the copper that lies in the opening to form single inlaid structures that include conducting interconnect lines and contact vias.

30. The method of claim 21, further comprising a method whereby multilevel conducting structures are fabricated by repeating the process described herein.