Integrated circuit device providing isolation between adjacent regions

• US 6,437,379 B2
• Filed: 05/22/2001
• Issued: 08/20/2002
• Est. Priority Date: 03/03/2000
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Dietrich W. Vook, Thomas Dungan, Thomas Edward Kopley
• Inventors: Vook, Dietrich W., Kopley, Thomas Edward, Dungan, Thomas
• Primary Examiner(s): Ho, Hoai V.
• Assistant Examiner(s): LE, DUNG ANH
• Application Number:
  US09/863,854
• Publication Number:
  US 20010023095A1
• Time in Patent Office: 455 Days
• Field of Search: 257/225, 257/233, 257/258, 257/291, 257/292, 257/369, 257/431, 257/435, 257/446, 257/444, 257/452, 257/459, 257/461
• US Class Current: 257/291
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

Claims

1. An integrated circuit having CMOS transistors comprising:

a substrate;

a first region along a surface of said substrate, said first region having an edge, said first region being a field oxide region;

a second region along said surface, said second region having a periphery which is adjacent to said edge of said first region;

a guard layer residing on said surface and following adjacency of said first and second regions, said guard layer extending onto only a peripheral portion of said second region;

wherein said second region includes said peripheral transition portion that is substantially free of a selected dopant and includes a remaining active portion in which said selected dopant is implanted, said peripheral transition portion being defined by said guard layer extending onto said second region.

2. The integrated circuit of claim 1 wherein said guard layer has a fixed connection to a source of a constant voltage.

3. The integrated circuit of claim 1 wherein said second region is a photodiode region.

4. The integrated circuit of claim 1 wherein said second region is a source/drain region of a MOSFET, said guard layer being contiguous with a gate of said MOSFET.