Semiconductor memory device with reduced orientation-dependent oxidation in trench structures

• US 6,437,381 B1
• Filed: 04/27/2000
• Issued: 08/20/2002
• Est. Priority Date: 04/27/2000
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG), International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jammy, Rajarao, Tews, Helmut H., Gruening, Ulrike
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/560,081
• Time in Patent Office: 845 Days
• Field of Search: 257/296, 257/297, 257/298, 257/301-305, 257/306
• US Class Current: 257/296
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A process for forming an oxide layer on a sidewall of a trench in a substrate. The process comprises the steps of forming the trench in the substrate, forming a nitride interface layer over a portion of the trench sidewall, forming an amorphous layer over the nitride interface layer, and oxidizing the amorphous layer to form the oxide layer. The process may be used, for example, to form a gate oxide for a vertical transistor, or an isolation collar. The invention also comprises a semiconductor memory device comprising a substrate, a trench in the substrate having a sidewall, an isolation collar comprising an isolation collar oxide layer on the trench sidewall in an upper region of the trench, and a vertical gate oxide comprising a gate oxide layer located on the trench sidewall above the isolation collar. The isolation collar oxide layer is disposed over an isolation collar nitride interface layer between the isolation collar oxide layer and the trench sidewall, the gate oxide layer is disposed over a gate nitride interface layer between the gate oxide layer and the trench sidewall, or both.

Claims

1. A deep trench isolation collar oxide layer produced by a process comprising the steps of:

(a) forming a trench having a sidewall in a substrate;

(b) forming a nitride interface layer over at least a portion of the trench sidewall;

(c) forming an amorphous silicon layer over the nitride interface layer;

(d) forming a nitride-oxynitride barrier layer over the amorphous silicon layer;

(e) etching away a portion of the nitride-oxynitride barrier layer to uncover a portion of the amorphous silicon layer desired to be oxidized for formation of the isolation collar;

(f) oxidizing the amorphous silicon layer to form the isolation collar oxide layer; and

(g) forming a node dielectric layer over the isolation collar oxide layer.

2. The deep trench isolation collar oxide layer of claim 1, wherein the oxide layer cross section has a periphery with a substantially uniform thickness.

3. The deep trench isolation collar oxide layer of claim 1, wherein the trench sidewalls are not faceted.

4. A semiconductor device comprising:

a substrate having a trench with a sidewall;

an isolation collar including an isolation collar oxide layer on the trench sidewall in an upper region of the trench;

a vertical gate oxide including a gate oxide layer on the trench sidewall in an upper region of the trench above the isolation collar;

at least one of (a) an isolation collar nitride interface layer disposed on the trench sidewall, with the isolation collar disposed over the isolation collar nitride interface layer, and (b) a gate nitride interface layer disposed on the trench sidewall, with the vertical gate oxide disposed over the gate nitride interface layer; and

wherein the trench sidewall, underlying at least one of said isolation collar nitride interface layer and said gate nitride interface layer further includes an oxide layer.

5. The semiconductor memory device of claim 4 wherein the semiconductor memory device comprises a DRAM device.

6. The semiconductor memory device of claim 4 wherein the isolation collar oxide layer and the gate oxide layer both comprise a silicon oxide and the substrate comprises a crystalline silicon wafer.

7. The semiconductor memory device of claim 4 wherein the isolation collar oxide layer disposed over the isolation collar nitride barrier layer has a thickness in a range of about 5 to about 20 nanometers, the gate oxide layer disposed over the gate nitride barrier layer has a thickness in a range of about 5 to about 10 nanometers, or both.

8. The semiconductor memory device of claim 7 wherein the gate oxide layer has a thickness of about 6 nanometers and is disposed over the gate nitride barrier layer.

9. The semiconductor memory device of claim 4 wherein the isolation collar oxide layer has a thickness of about 10 nanometers and is disposed over the isolation collar nitride barrier layer.

10. The semiconductor memory device of claim 4 wherein at least one of the isolation collar nitride interface layer and the gate nitride interface layer has thickness in a range of about 0.5 to about 2 nanometers.

11. The semiconductor memory device of claim 4 wherein at least one of the isolation collar nitride interface layer and the gate nitride interface layer has thickness of about 1 nanometer.

12. The semiconductor memory device of claim 4, wherein at least one of the vertical gate oxide layer or the isolation collar oxide layer has a periphery with a substantially uniform thickness.

13. The semiconductor memory device of claim 4, wherein the trench sidewalls are not faceted.