Method for creating thick oxide on the bottom surface of a trench structure in silicon

• US 6,437,386 B1
• Filed: 08/16/2000
• Issued: 08/20/2002
• Est. Priority Date: 08/16/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Murphy, James J., Hurst, Henry W.
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Wilson, Scott R.
• Application Number:
  US09/640,954
• Time in Patent Office: 734 Days
• Field of Search: 257/301, 438/243, 438/386
• US Class Current: 257/301
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the efficiency of the semiconductor device and prolonging its life.

Claims

1. A gate isolation structure of a semiconductor device, comprising:

a trench formed in a silicon substrate, said trench defined by sidewalls and a curved, non-flat bottom; and

a dielectric layer formed on the sidewalls and bottom of the trench, said dielectric layer having a thickness transition region that smoothly tapers in thickness from a first thickness on the sidewalls of the trench to a second and greater thickness at the bottom of the trench.

2. The structure of claim 1 wherein the dielectric layer further comprises a gate oxide layer.

3. The structure of claim 1 wherein dielectric layer substantially conforms to the bottom of the trench.

4. A trench field affect transistor formed on a silicon substrate, the trench comprising:

a trench formed in a silicon substrate, said trench defined by sidewalls and a curved, non-flat bottom;

a dielectric layer formed on the sidewalls and bottom of the trench, said dielectric layer having a thickness transition region that smoothly tapers in thickness from a first thickness on the sidewalls of the trench to a second and greater thickness at the bottom of the trench; and

a gate conductive material substantially filling the trench.

5. The transistor of claim 4 wherein the dielectric layer further comprises a gate oxide layer.

6. The transistor of claim 4 further comprising a pair of doped source regions positioned adjacent to and on opposite sides of the trench forming a source electrode of the field effect transistor, and the substrate forming a drain electrode of the field effect transistor.