Semiconductor structures with trench contacts

• US 6,437,399 B1
• Filed: 02/04/2000
• Issued: 08/20/2002
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Huang, Qin
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US09/498,476
• Time in Patent Office: 928 Days
• Field of Search: 257/377, 257/329, 257/330, 257/331, 257/332, 257/328, 257/346
• US Class Current: 257/329
• CPC Class Codes: H01L 29/41716 Cathode or anode electrodes for thyristors
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pitch is reduced relative to conventional structures.

Claims

1. A FET semiconductor structure comprising:

a polysilicon filled trench lined with a gate oxide bounding a source region, said source region overlying and in contact with a channel region;

a metal filled trench in contact with both the source and channel regions, wherein the metal filled trench extends downwardly to a trench floor disposed within the channel region so that the only substantial contact of the metal filled trench with the channel region is along a vertical boundary of said channel region; and

a region having a higher impurity concentration than the channel region, said region with the higher impurity concentration lying substantially directly beneath and in contact with the floor of the metal filled trench and extending laterally to merge with an adjoining portion of the channel region.

2. The semiconductor structure of claim 1 wherein the metal filled trench is laterally spaced from the polysilicon filled trench.

3. The semiconductor structure of claim 2 wherein the metal filled trench is shallower than the polysilicon filled trench.

4. The semiconductor structure of claim 1 wherein the region having a higher impurity region than the channel region extends to a depth at least substantially equal to the depth of the polysilicon filled trench.

5. The semiconductor structure of claim 4 wherein the region having a higher impurity region than the channel region extends to a depth greater than the depth of the polysilicon filled trench.

6. The semiconductor structure of claim 1 wherein the source and channel regions form a substantially horizontal PN junction.

7. The semiconductor structure of claim 1 further comprising an insulating layer overlying the polysilicon filled trench.

8. The semiconductor structure of claim 7 wherein the insulating layer comprises borophosphosilicate glass.

9. The semiconductor structure of claim 1 embodied in a trench IGBT.

10. A FET semiconductor structure comprising:

a wafer comprising a polysilicon filled trench lined with a gate oxide bounding a source region, said source region overlying and in contact with a channel region, said channel region overlying and bordering a region of high impurity concentration so that there is a material area of contact between said channel region and said region of high impurity concentration; and

a metal filled trench in contact with both the source and channel regions, wherein the metal filled trench has areas of contact with the source and channel regions that are generally coplanar with one another, and wherein the metal filled trench extends downwardly into the wafer into contact with the channel region rather than laterally along the wafer surface into contact with the channel region so that the only substantial contact of the metal filled trench with the channel region is along a vertical boundary of said channel region.

11. A semiconductor structure comprising:

a wafer containing a horizontally disposed gate, said gate bounding a source region, said source region overlying and in contact with a channel region, said channel region overlying and bordering a region of high impurity concentration so that there is a material area of contact between said channel region and said region of high impurity concentration; and

a metal having areas of contact along vertical boundaries of both the source and channel regions, said areas of contact with said source and channel regions being generally coplanar with one another, said metal extending vertically into said wafer to contact said region of high impurity concentration.

12. The semiconductor structure of claim 11 embodied in a planar MOSFET.

13. The semiconductor structure of claim 11 embodied in a planar IGBT.

14. The semiconductor structure of claim 11 embodied in a planar MCT.

15. The semiconductor structure of claim 11 wherein said metal comprises a vertical metal filled trench disposed substantially above said region of high impurity concentration.