Structure and method for improved isolation in trench storage cells

• US 6,437,401 B1
• Filed: 04/03/2001
• Issued: 08/20/2002
• Est. Priority Date: 04/03/2001
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Infineon Technologies AG, International Business Machines Corporation
• Inventors: Rahn, Stephen, Tews, Helmut, Mandelman, Jack A., Knorr, Andreas, Wise, Michael, Kudelka, Stephan
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/824,957
• Time in Patent Office: 504 Days
• Field of Search: 257/330, 257/331, 257/328
• US Class Current: 257/330
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

Claims

1. Semiconductor apparatus comprising:

a semiconductor body defining a trench therein and being of a first conductivity type;

first and second semiconductor regions of a second conductivity type that is opposite the first conductivity type, said regions being located within the semiconductor body and being separated by a portion of the semiconductor body;

each of the first and second semiconductor regions having a section thereof which defines portions of a wall of the trench;

a part of the portion of the semiconductor body between the first and second semiconductor regions defining a void which extends around the perimeter of the trench;

the wall of the trench being lined with an insulating layer that separates the void from the trench and separates the second semiconductor region from the trench; and

the trench being filled with a conductive material that contacts the section of the first semiconductor region that defines a portion of the wall of the trench.

2. The semiconductor body of claim 1 further comprising a second insulating layer which lines the portions of the semiconductor body that define the void.

3. The semiconductor body of claim 1 wherein the void is located near the position in the portion of the semiconductor body between the first and second semiconductor regions where the peak in impurity concentration of this portion exists.

4. The semiconductor body of claim 1 wherein the void is located at the position in the portion of the semiconductor body between the first and second semiconductor regions where the peak in impurity concentration of this portion exists.

5. A transistor-capacitor memory cell comprising:

a semiconductor body defining a trench therein and being of a first conductivity type;

first, second, and third semiconductor regions of a second conductivity type that is opposite the first conductivity type, said regions being located within the semiconductor body and being separated by portions of the semiconductor body;

the first and second semiconductor regions being first and second input/output regions of the transistor of the memory cell;

a gate of the transistor being located between a portion of the semiconductor body between the first and second input/output regions and being separated therefrom by a gate dielectric layer;

each of the second and third semiconductor regions having a section thereof which defines portions of a wall of the trench;

a part of the portion of the semiconductor body between the second and third semiconductor regions defining a void which extends around the perimeter of the trench;

portions of the wall of the trench being lined with a first insulating layer that separates the void from the trench and separates the third semiconductor region from the trench;

the insulation lined trench being filled with a conductive material that contacts the portion of the second semiconductor region that defines a portion of the wall of the trench; and

the conducive material, insulating layer, and third semiconductor region serving as the capacitor of the memory cell.

6. The transistor-capacitor memory cell of claim 5 further comprising a second insulating layer which lines the portions of the semiconductor body that define the void.

7. The transistor-capacitor memory cell of claim 5 wherein the void is located near the position in the portion of the semiconductor body between the second and third semiconductor regions where the peak in impurity concentration of this portion exists.

8. The transistor-capacitor memory cell of claim 5 wherein the void is located at the position in the portion of the semiconductor body between the second and third semiconductor regions where the peak in impurity concentration of this portion exists.

9. Semiconductor apparatus comprising:

a semiconductor substrate;

the semiconductor substrate defining a trench therein which has at least one wall;

a first n+ type conductivity region abutting the wall of the trench at a lower portion of said trench;

a first dielectric layer covering the part of the wall of said trench and being located over the portion of the first n+ type conductivity region;

a second n+ type conductivity region abutting at least one of the wall in an upper portion of said trench;

a p-type conductivity region within said semiconductor substrate positioned between said first and second n+ type conductivity diffusion regions;

a second dielectric layer covering portions of the wall of said trench positioned between said first and second n+ type conductivity diffusion regions;

a portion of the p-type conductivity region defining a continuous void therein which intersects the wall of the trench and encircles the perimeter of said trench and is positioned between said first and second n+ type conductivity diffusion regions; and

a conductive material disposed within said dielectrically lined trench.

10. The semiconductor structure of claim 9 wherein said first n+ type conductivity diffusion region is a first electrode of a capacitor and walls of the portion of the semiconductor substrate which define the void are lined with a third dielectric layer.

11. The semiconductor structure of claim 9 wherein said first dielectric layer is the insulator of a capacitor.

12. The semiconductor structure of claim 9 wherein said second n+ diffusion region is an input/output region of a field effect transistor.

13. The semiconductor structure of claim 9 wherein said p-type doped region is a p-well of a memory array.

14. The semiconductor structure of claim 9 wherein said conductive material disposed within said trench is a second electrode of a capacitor.

15. The semiconductor structure of claim 14 wherein said second electrode of the capacitor is n+ type conductivity polysilicon.

16. The semiconductor structure of claim 9 wherein said void is less than about 50 nm in depth from a surface of said semiconductor substrate.

17. The semiconductor structure of claim 16 wherein said void is between about 20 and 40 nm in depth from a surface of said semiconductor substrate.

18. The semiconductor structure of claim 9 wherein said dielectric material lining said void is between about 5nm and 15 nm thick.

19. The semiconductor structure of claim 9 wherein said void about 100 nm or less in height.

20. The semiconductor structure of claim 9 wherein said void is between about 40 nm and 80 nm in height.

21. The semiconductor structure of claim 9 wherein said first and second n+ type conductivity diffusion regions are vertically separated by less than about 1 μ

m.

22. The semiconductor structure of claim 13 wherein a peak of impurity concentration of said p-well is positioned about 300 nm above said first n+ type conductivity diffusion region.

23. The semiconductor structure of claim 22 wherein said void is positioned about at the depth of said peak of the impurity concentration of said p-well.

24. The semiconductor structure of claim 23 wherein said void is positioned within about 200 nm of said peak of the impurity concentration of said p-well.