Structure and method for improved isolation in trench storage cells
First Claim
1. Semiconductor apparatus comprising:
- a semiconductor body defining a trench therein and being of a first conductivity type;
first and second semiconductor regions of a second conductivity type that is opposite the first conductivity type, said regions being located within the semiconductor body and being separated by a portion of the semiconductor body;
each of the first and second semiconductor regions having a section thereof which defines portions of a wall of the trench;
a part of the portion of the semiconductor body between the first and second semiconductor regions defining a void which extends around the perimeter of the trench;
the wall of the trench being lined with an insulating layer that separates the void from the trench and separates the second semiconductor region from the trench; and
the trench being filled with a conductive material that contacts the section of the first semiconductor region that defines a portion of the wall of the trench.
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Accused Products
Abstract
A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.
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Citations
24 Claims
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1. Semiconductor apparatus comprising:
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a semiconductor body defining a trench therein and being of a first conductivity type;
first and second semiconductor regions of a second conductivity type that is opposite the first conductivity type, said regions being located within the semiconductor body and being separated by a portion of the semiconductor body;
each of the first and second semiconductor regions having a section thereof which defines portions of a wall of the trench;
a part of the portion of the semiconductor body between the first and second semiconductor regions defining a void which extends around the perimeter of the trench;
the wall of the trench being lined with an insulating layer that separates the void from the trench and separates the second semiconductor region from the trench; and
the trench being filled with a conductive material that contacts the section of the first semiconductor region that defines a portion of the wall of the trench. - View Dependent Claims (2, 3, 4)
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5. A transistor-capacitor memory cell comprising:
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a semiconductor body defining a trench therein and being of a first conductivity type;
first, second, and third semiconductor regions of a second conductivity type that is opposite the first conductivity type, said regions being located within the semiconductor body and being separated by portions of the semiconductor body;
the first and second semiconductor regions being first and second input/output regions of the transistor of the memory cell;
a gate of the transistor being located between a portion of the semiconductor body between the first and second input/output regions and being separated therefrom by a gate dielectric layer;
each of the second and third semiconductor regions having a section thereof which defines portions of a wall of the trench;
a part of the portion of the semiconductor body between the second and third semiconductor regions defining a void which extends around the perimeter of the trench;
portions of the wall of the trench being lined with a first insulating layer that separates the void from the trench and separates the third semiconductor region from the trench;
the insulation lined trench being filled with a conductive material that contacts the portion of the second semiconductor region that defines a portion of the wall of the trench; and
the conducive material, insulating layer, and third semiconductor region serving as the capacitor of the memory cell. - View Dependent Claims (6, 7, 8)
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9. Semiconductor apparatus comprising:
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a semiconductor substrate;
the semiconductor substrate defining a trench therein which has at least one wall;
a first n+ type conductivity region abutting the wall of the trench at a lower portion of said trench;
a first dielectric layer covering the part of the wall of said trench and being located over the portion of the first n+ type conductivity region;
a second n+ type conductivity region abutting at least one of the wall in an upper portion of said trench;
a p-type conductivity region within said semiconductor substrate positioned between said first and second n+ type conductivity diffusion regions;
a second dielectric layer covering portions of the wall of said trench positioned between said first and second n+ type conductivity diffusion regions;
a portion of the p-type conductivity region defining a continuous void therein which intersects the wall of the trench and encircles the perimeter of said trench and is positioned between said first and second n+ type conductivity diffusion regions; and
a conductive material disposed within said dielectrically lined trench. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification