Semiconductor-on-insulator transistor with recessed source and drain

• US 6,437,404 B1
• Filed: 08/10/2000
• Issued: 08/20/2002
• Est. Priority Date: 08/10/2000
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lin, Ming-Ren, Xiang, Qi, Long, Wei
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/636,239
• Time in Patent Office: 740 Days
• Field of Search: 257/347, 257/349, 257/375, 257/382, 257/408, 438/149, 438/479, 438/517
• US Class Current: 257/347
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.

Claims

1. A semiconductor-on-insulator transistor device comprising:

a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion;

a gate atop the semiconductor layer; and

silicide regions between the top surface and at least part of respective of the deep portions;

wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate;

wherein the silicide regions include a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain; and

wherein the silicide regions are at least partially in contact with the deep portions.

2. A semiconductor-on-insulator transistor device comprising:

a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion;

a gate atop the semiconductor layer; and

silicide regions between the top surface and at least part of respective of the deep portions;

wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate;

wherein the silicide regions include a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain; and

wherein the source and drain silicide regions are at least partially atop the shallow portion.

3. The transistor device of claim 2, further comprising a buried semiconductor region at least partially between one of the silicide regions and a corresponding of the deep portions.

4. The transistor device of claim 2, wherein the silicide regions each have a maximum thickness of at least 200 Angstroms.

5. The transistor device of claim 2, wherein the semiconductor layer has a thickness of between 500 and 5000 Angstroms.

6. The transistor device of claim 2, wherein the semiconductor layer has a thickness less than about ⅓

of a length of the gate.

7. The transistor device of claim 2, wherein the gate includes a metal gate electrode.

8. The transistor device of claim 2, wherein the semiconductor layer includes a fully depleted channel region.

9. The transistor device of claim 2, wherein the shallow portion is wider than the gate.

10. The transistor device of claim 2, wherein the buried insulator layer is a buried oxide layer.

11. The transistor device of claim 10, wherein the semiconductor layer is a silicon layer and the buried oxide layer is a buried silicon oxide layer.

12. The transistor device of claim 10, wherein the buried insulator layer is a continuous layer.

13. The transistor device of claim 10, wherein the buried insulator layer includes transition portions between the shallow portion and the deep portions.

14. The transistor device of claim 13, wherein the transition portions each have a curved shape.

15. The transistor device of claim 13, wherein the source and drain silicide portions are in contact with respective of the transition portions.

16. The transistor device of claim 2, wherein the buried insulator layer has substantially uniform thickness.

17. The transistor device of claim 2, wherein the shallow portion is substantially parallel to the top surface, the semiconductor layer thereby having a substantially uniform thickness.

18. The transistor device of claim 2, wherein the source and drain silicide portions are in contact with the shallow portion of the buried insulator layer.

19. The transistor device of claim 2, wherein the source and the drain include respective source and drain extensions, and wherein the source and drain extensions are in contact with the shallow portion of the buried insulator layer.

20. A semiconductor-on-insulator transistor device comprising:

a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion;

a gate atop the semiconductor layer; and

a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain;

wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate;

wherein the source and the drain include respective source and drain extensions, and wherein the source and drain extensions are in contact with the shallow portion of the buried insulator layer;

wherein the suicide regions are atop the shallow portion of the buried insulator layer; and

wherein the suicide regions are in contact with the shallow portion.

21. The transistor device of claim 20, wherein the buried insulator layer includes transition portions between the shallow portion and the deep portions.

22. The transistor device of claim 21, wherein the silicide regions are atop respective of the transition portions.

23. The transistor device of claim 20, wherein the semiconductor layer includes a fully depleted channel layer.

24. A semiconductor-on-insulator transistor device comprising:

a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion;

a gate atop the semiconductor layer; and

a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain;

wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate;

wherein the source and the drain include respective source and drain extensions, and wherein the source and drain extensions are in contact with the shallow portion of the buried insulator layer;

wherein the silicide regions are atop the shallow portion of the buried insulator layer;

wherein the buried insulator layer includes transition portions between the shallow portion and the deep portions;

wherein the silicide regions are atop respective of the transition portions; and

wherein the silicide regions are in contact with respective of the transition portions.

25. The transistor device of claim 24, wherein the transition portions each have a curved shape.

26. The transistor device of claim 25, wherein the silicide regions are in contact with the shallow portion.

27. The transistor device of claim 26, wherein the semiconductor layer includes a fully depleted channel layer.

28. The transistor device of claim 26, wherein the buried insulator layer includes a semiconductor oxide.