Semiconductor device

• US 6,437,409 B2
• Filed: 02/13/2001
• Issued: 08/20/2002
• Est. Priority Date: 02/14/2000
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Advanced Technologies Inc. (f/k/a Tessera Advanced Technologies, Inc.) (Adeia Inc.)
• Original Assignee: NEC Corporation
• Inventors: Fujii, Hiroki
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/781,252
• Publication Number:
  US 20010013626A1
• Time in Patent Office: 553 Days
• Field of Search: 257/379, 257/528, 257/531, 257/630, 438/238
• US Class Current: 257/379
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 28/10 Inductors

Abstract

The first shield pattern is provided between an inductor and the surface of a semiconductor substrate under the inductor. The first shield pattern has plural concave slittings from the side of the edge toward the inside. The second shield pattern provides a convex area which is located on the surface of the semiconductor substrate in correspondence with the slitting wherin metallic silicide is formed and a connection area which is provided on the surface of the semiconductor substrate and in which metallic silicide is formed for connecting plural convex areas.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming a first insulating layer on a substrate to expose a part of said substrate;

forming a first shield pattern over said first insulating layer;

forming a second shield pattern on said part of said substrate;

forming a second insulating layer; and

forming an inductor pattern on said second insulating layer;

wherein said first shield pattern has a concave slit from an edge of said first shield pattern toward a center of said first shield pattern.

2. The method of manufacturing a semiconductor device as claimed in claim 1,

wherein said first shield pattern is comprising a first conductive layer and a second conductive layer on said first conductive layer.

3. The method of manufacturing a semiconductor device as claimed in claim 2, wherein said step of forming said first shield pattern is comprising forming said a first conductive layer on said first insulating layer, forming a sidewall on said first conductive layer, and forming said second conductive layer on said first conductive layer.

4. The method of manufacturing a semiconductor device as claimed in claim 1,

wherein said substrate is comprising an mductor area and a transistor area, and said first insulating layer is comprising an element isolating layer at said inductor area and a gate insulating layer at said transistor area.

5. The method of manufacturing a semiconductor device as claimed in claim 4, wherein said step of forming said first insulating layer is comprising forming the first insulating layer, patterning said first insulating layer to expose a first part of said substrate at said inductor area, patterning said first insulating layer to expose a second part of said substrate at said transistor area, and forming a gate insulating layer on said second part of said substrate on said transistor area.

6. The method of manufacturing a semiconductor device as claimed in claim 5, wherein said first shield pattern is comprising a first conductive layer and a second conductive layer on said first conductive layer.

7. The method of manufacturing a semiconductor device as claimed in claim 6, wherein said step of forming said first shield pattern is comprising forming said first conductive layer on said element isolating layer at said inductor area, forming said first conductive layer on said gate insulating layer at said transistor area, forming a sidewall on said first conductive layer, and forming said second conductive layer on said first conductive layer.

8. The method of manufacturing a semiconductor device as claimed in claim 6, wherein said inductor pattern is formed at said inductor area.

9. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said substrate is comprising an inductor area and a transistor area, and

wherein said step of forming said first insulating layer is comprising forming the first insulating layer, patterning said first insulating layer to expose a first part of said substrate on said inductor area and a second part of said substrate on said transistor area, forming gate insulating layer on said first part of said substrate on said inductor area to expose at a region corresponding to said concave slit, and forming a gate insulating layer on said second part of said substrate on said transistor area.

10. The method of manufacturing a semiconductor device as claimed in claim 9, wherein said shield pattern is comprising a first conductive layer and a second conductive layer on said first conductive layer.

11. The method of manufacturing a semiconductor device as claimed in claim 10, wherein said step of forming said first shield pattern is comprising forming said first conductive layer on said gate insulating layer at said inductor area, forming said first conductive layer on said gate insulating layer at said transistor area, forming a sidewall on said first conductive layer, and forming said second conductive layer on said first conductive layer.

12. The method of manufacturing a semiconductor device as claimed in claim 11, wherein said inductor pattern is formed at said inductor area.

13. The method of manufacturing a semiconductor device as claimed in claim 9 further comprising:

forming a contact hole in said second insulating layer to expose said concave slit of said second shield pattern and said first shield pattern where is adjacent to said concave slit.

14. A semiconductor device comprising:

a substrate;

a first insulating layer on said substrate;

a first shield pattern, said first shield pattern over said first insulating layer, having a concave slit from an edge of said first shield pattern toward a center of said first shield pattern;

a second insulating layer on said first shield pattern;

a second shield pattern on said substrate, said second shield pattern being formed at a region under said concave slit of said first shield pattern; and

an inductor on said second insulating layer;

wherein said first insulating layer has a concave slit at a region under said concave slit of said first shield pattern.

15. The semiconductor device as claimed in claim 14, wherein said first shield pattern and second shield pattern are connected by at least one through hole which is formed in said first insulating layer.

16. The semiconductor device as claimed in claim 15, wherein said first shield pattern and second shield pattern a connected by a ground connection to a ground power source.

17. A semiconductor device comprising:

a substrate;

a first shield pattern on said substrate, said shield pattern having a concave slit from an edge of said first shield pattern toward a center of said first shield pattern;

a first insulating layer on said concave slit;

a second shield pattern on said first insulating layer;

a second insulating layer on said second shield pattern; and

an inductor on said second insulating layer.

18. The semiconductor device as claimed in claim 17, wherein said first shield pattern and second shield pattern arm connected by at least one through hole which is formed in said first insulating layer.

19. The semiconductor device as claimed in claim 18, wherein said first shield pattern and second shield pattern are connected by a ground connection to a ground power source.

20. A semiconductor device comprising:

a semiconductor substrate;

a first insulating layer formed on said semiconductor substrate;

a first shield layer formed over said first insulating layer;

a first slit selectively formed in said first shield layer to thereby define a part of said semiconductor substrate that is free from being covered with said first shield layer;

a second insulating layer covering said first shield layer and said first insulating layer;

an inductor formed on said second insulating layer; and

a second shield layer provided separately from said first shield layer to cover said part of said semiconductor substrate.

21. The semiconductor device as claimed in claim 20, wherein said second shield layer under said first insulating layer in contact with said part of said semiconductor substrate.

22. The semiconductor device as claimed in claim 21, wherein said second shield layer comprises a silicide layer.

23. A method of manufacturing a semiconductor device comprising:

forming a first insulating layer on a substrate to expose a part of said substrate;

forming a first shield pattern over said first insulating layer;

forming a second shield pattern on said part of said substrate;

forming a second insulating layer; and

forming an inductor pattern on said second insulating layer;

wherein said first shield pattern has a concave slit, said concave slit defined by at least a first edge and second edge of said first shield pattern, wherein a lateral distance spans between said first and second edges, said concave slit positioned from an edge of said first shield pattern laterally toward a center of said first shield pattern.

24. A semiconductor device comprising:

a substrate;

a first insulating layer on said substrate;

a first shield pattern, said first shield pattern over said first insulating layer, having a concave slit, said concave slit defined by at least a first edge and second edge of said first shield pattern, wherein a lateral distance spans between said first and second edges, said concave slit positioned from an edge of said first shield pattern laterally toward a center of said first shield pattern;

a second insulating layer on said first shield pattern;

a second shield pattern on said substrate, said second shield pattern being formed at a region under said concave slit of said first shield pattern; and

an inductor on said second insulating layer;

wherein said first insulating layer has a concave slit at a region under said concave slit of said first shield pattern.

25. A semiconductor device comprising:

a substrate;

a first shield pattern on said substrate, said shield pattern having a concave slit, said concave slit defined by at least a first edge and second edge of said first shield pattern, wherein a lateral distance spans between said first and second edges, said concave slit positioned from an edge of said first shield pattern laterally toward a center of said first shield pattern;

a first insulating layer on said concave slit;

a second shield pattern on said first insulating layer;

a second insulating layer on said second shield pattern; and

an inductor on said second insulating layer.