Interlayer dielectric with a composite dielectric stack

• US 6,437,444 B2
• Filed: 11/29/2000
• Issued: 08/20/2002
• Est. Priority Date: 12/19/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Andideh, Ebrahim
• Primary Examiner(s): Flynn, Nathan
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US09/726,504
• Publication Number:
  US 20010000012A1
• Time in Patent Office: 629 Days
• Field of Search: 438/624, 438/675, 438/386, 438/783, 438/253, 257/752, 257/703, 257/700, 257/758, 257/750, 257/701, 257/753, 257/760, 257/759
• US Class Current: 257/760
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051

Abstract

A method of forming an interlayer dielectric on a semiconductor device is disclosed. First, a phosphorous doped oxide layer is deposited on the semiconductor device to fill gaps and provide phosphorous for gettering. Then, an undoped oxide layer is deposited and planarized using chemical mechanical polishing (CMP). The undoped oxide layer is denser than the phosphorous doped oxide layer, so the undoped oxide layer can be polished more uniformly than the phosphorous doped oxide layer and can serve as a polish stop for a subsequent tungsten plug polish. Also, the denser undoped oxide layer serves as a more effective moisture barrier than the doped oxide layer. Overall fabrication process complexity can be reduced by performing both oxide depositions in a single operation with no intervening densification or CMP steps.

Claims

1. An interlayer dielectric between a layer of semiconductor devices and layer of interconnects comprising:

a planarized insulating layer; and

an unplanarized insulating layer comprising phosphorous between said planarized insulating layer and said semiconductor devices, said unplanarized insulating layer being less dense than said planarized insulating layer.

2. The interlayer dielectric of claim 1, further comprising a layer of silicon nitride between said semiconductor devices and said unplanarized insulating layer.

3. The interlayer dielectric of claim 1, said unplanarized insulating layer having a higher dielectric constant than said planarized insulating layer.

4. The interlayer dielectric of claim 1, said unplanarized insulating layer comprising between one percent to eight percent phosphorous by weight.

5. The interlayer dielectric of claim 1, wherein the thickness of unplanarized insulating layer is approximately 100 to approximately 5,000 angstroms.

6. The interlayer dielectric of claim 1, wherein the thickness of planarized insulating layer is approximately 500 to approximately 10,000 angstroms.