Multi-level cache controller

• US 6,437,789 B1
• Filed: 02/19/1999
• Issued: 08/20/2002
• Est. Priority Date: 02/19/1999
• Status: Expired due to Fees

• Current Assignee: Evans & Sutherland Computer Corp. (Elevate Entertainment, Inc.)
• Original Assignee: Evans & Sutherland Computer Corp. (Elevate Entertainment, Inc.)
• Inventors: Tidwell, Reed, Pimentel, Gary
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/253,474
• Time in Patent Office: 1,278 Days
• Field of Search: 345/531, 345/532, 345/536-538, 345/557, 345/558, 345/556, 711/105, 711/100, 711/118, 711/131, 711/138-140
• US Class Current: 345/557
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A method and apparatus for accessing a cache memory of a computer graphics system, the apparatus including a frame buffer memory having a graphics memory for storing pixel data for ultimate supply to a video display device, a read cache memory for storing data received from the graphics memory, and a write cache memory for storing data received externally of the frame buffer and data that is to be written into the graphics memory. Also included is a frame buffer controller for controlling access to the graphics memory and read and write cache memories. The frame buffer controller includes a cache first in, first out (FIFO) memory pipeline for temporarily storing pixel data prior to supply thereof to the cache memories.

Claims

1. In a computer graphics system for developing video images for display on a video display device, a cache control system, comprising:

a frame buffer memory having;

a first memory for storing pixel data for ultimate supply to the video display device, and

a cache memory for storing data received from the first memory, data which is to be written into the first memory, and data received from a cache controller, and

a cache controller coupled to the cache memory for controlling access thereto, the cache controller comprising;

a cache first in, first out (FIFO) memory pipeline for temporarily storing pixel data prior to supply thereof to the cache memory and adapted to temporarily store cache commands for supplying to the cache memory, along with any pixel data then stored in the cache FIFO memory, to cause the cache memory to store said any pixel data, to store data received from the first, or write data into the first memory, wherein said cache controller further includes a first command first in, first out (FIFO) memory for temporarily storing first commands for supply to the first memory to cause the first memory to store pixel data received from cache memory or write data into the cache memory.

2. In a computer graphics system for developing video images for display on a video display device, a cache control system comprising

a frame buffer memory having

a first memory for storing pixel data for ultimate supply to the video display device, and

a cache memory for storing data received from the first memory, data which is to be written into the first memory, and data received from a cache controller, and

a cache controller, coupled to the cache memory for controlling access thereto, the cache controller comprising:

a cache first in, first out (FIFO) memory pipeline for temporarily storing pixel data prior to supply thereof to the cache memory and adapted to temporarily store cache commands for supplying to the cache memory, along with any pixel data then stored in the cache FIFO memory, to cause the cache memory to store said any pixel data, to store data received from the first memory, or write data into the first memory, wherein said cache controller further includes a first command first in, first out (FIFO) memory for temporarily storing first commands for supply to the first memory to cause the first memory to store pixel data received from the cache memory or write data into the cache memory; and

an interlock means, coupled to the cache FIFO memory and the first command FIFO memory, for controlling and synchronizing the reading of pixel data and cache commands from the cache FIFO memory, and the reading of first commands from the first command FIFO memory, such that for any particular pixel data access to the frame buffer memory, the first commands are read from the first command FIFO memory prior to the reading of the cache commands and pixel data from the cache FIFO memory.

3. A cache control system as in claim 2 wherein said interlock means is adapted to cause the reading of pixel data and cache commands from the cache FIFO memory if no first commands are stored in the first command FIFO memory.

4. A cache control system as in claim 3 wherein said interlock means includes a sync counter that increments when the last of the first commands stored in the first command FIFO memory is read, and decrements when, following the incrementing, the first of the corresponding cache commands stored in the cache FIFO memory is read.

5. A cache memory control system for controlling accesses to a frame buffer of a computer graphics display system which generates images from pixel data for display on a video display unit, said control system including:

a frame buffer memory comprising

a graphics memory for storing pixel data for supply to the video display unit to enable generation of images for display,

a read cache memory for storing data received from the graphics memory, and

a write cache memory for storing data received externally of the frame buffer and data that is to be written into the graphics memory, and

a frame buffer controller for controlling writing of data into and reading of data from the frame buffer memory, and the transfer of data between the graphics memory and read cache memory, and between the graphics memory and write cache memory, wherein said frame buffer controller includes

a cache first in, first out (FIFO) memory pipeline for temporarily storing pixel data and cache commands prior to supply thereof to the read and write cache memories to cause the read cache memory to store data received from the graphics memory, and cause the write cache memory to store the pixel data to be written into the graphics memory;

a graphics command first in, first out (FIFO) memory for temporarily storing graphics commands for supply to the graphics memory to cause the graphics memory to store pixel data received from the write cache memory or write data into the read cache memory and write cache memory.

6. A cache memory control system for controlling accesses to a frame buffer of a computer graphics display system which generates images from pixel data for display on a video display unit, said control system including

a frame buffer memory comprising

a graphics memory for storing pixel data for supply to the video display unit to enable generation of images for display,

a read cache memory for storing data received from the graphics memory, and

a write cache memory for storing data received externally of this frame buffer and data that is to be written into the graphics memory, and

a frame buffer controller for controlling writing of data into and reading of data from the frame buffer memory, and the transfer of data between the graphics memory and read cache memory, and between the graphics memory and write cache memory, said frame buffer controller includes

a cache first in, first out (FIFO) memory pipeline for temporarily storing pixel data and cache commands prior to supply thereof to the read and write cache memories to cause the read cache memory to store data received from the graphics memory, and cause the write cache memory to store the pixel data to be written into the graphics memory;

a graphics command first in, first out (FIFO) memory for temporarily storing graphics commands for supply to the graphics memory to cause the graphics memory to store pixel data received from the write cache memory or write data into the read cache memory and write cache memory; and

interlock logic coupled to the cache FIFO memory and graphics FIFO memory for causing the reading of graphics commands to the graphics memory, for any particular pixel data access, prior to the reading of corresponding cache commands and pixel data to the read and write cache memories.

7. A control system as in claim 6 wherein said interlock logic is adapted to allow graphics memory accesses from the graphics FIFO memory for successive pixel data, while the read and write cache memories are being accessed from the cache FIFO memory for current pixel data.

8. A method for controlling access to a cache memory system of a computer graphics system for developing video images for display on a video display device, said method comprising the steps of:

(1) providing a frame buffer having a separate read cache memory for storing data received from a graphics system memory, and a separate write cache memory for storing data that is to be written to the graphics system memory;

(2) storing pixel data in a cache first in, first out (FIFO) memory pipeline for supply to the write cache memory;

(3) storing cache commands in the cache FIFO memory for supply, along with the pixel data, to the read and write cache memories,

(4) storing graphics commands in a graphics first in, first out (FIFO) memory for supply to the graphics system memory, and

(5) providing an interlock unit for controlling and synchronizing the reading of pixel data and cache commands from the cache FIFO memory, and the reading of graphics commands from the graphics FIFO memory so that for any pixel data access, the graphics commands are read prior to the reading of the corresponding pixel data and cache commands.

9. A method for controlling access to a cache memory system of a computer graphics system for developing video images for display on a video display device, said method comprising the steps of:

(1) providing a frame buffer having a separate read cache memory for storing data received from a graphics system memory, and a separate write cache memory for storing data that is to be written to the graphics system memory;

(2) storing pixel data in a cache first in, first out (FIFO) memory pipeline for supply to the write cache memory;

(3) storing cache commands in the cache FIFO memory for supply, along with the pixel data, to the read and write cache memories,

(4) storing graphics commands in a graphics first in, first out (FIFO) memory for supply to the graphics system memory,

(5) assigning a flag to data in the cache FIFO memory that needs to be written back to the graphics system memory; and

(6) preventing certain data from being written back to the graphics system memory.

11. The method as defined in claim 9 further comprising the step of:

(12) supplying the pixel data from cache FIFO memory to the write cache memory if a hit condition does not exist (miss) in cache memory.

10. A method for controlling access to a cache memory system of a computer graphics system for developing video images for display on a video display device, said method comprising the steps of:

(1) providing a frame buffer having a separate read cache memory for storing data received from a graphics system memory, and a separate write cache memory for storing data that is to be written to the graphics system memory;

(2) storing pixel data in a cache first in, first out (FIFO) memory pipeline for supply to the write cache memory.

(3) storing cache commands in the cache FIFO memory for supply, along with the pixel data, to the read and write cache memories,

(4) storing graphics commands in a graphics first in, first out (FIFO) memory for supply to the graphics system memory,

(5) storing flags indicating whether the different locations in the read cache memory and write cache memory contain pixel data,

(6) determining from the flags, for pixel data to be loaded in cache FIFO memory, first whether a hit condition exists in write cache memory and second whether a hit condition exists in read cache memory, and

(7) preventing the reading of data from the graphics system memory into the read cache memory if a hit condition exists in write cache memory, and causing the writing of pixel data from the write cache memory to the graphics system memory.