Memory cell configuration

• US 6,438,022 B2
• Filed: 05/10/2001
• Issued: 08/20/2002
• Est. Priority Date: 11/10/1998
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Infineon Technologies AG
• Inventors: Haneder, Thomas-Peter, Hofmann, Franz, Schlösser, Till, Krautschneider, Wolfgang
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/854,259
• Publication Number:
  US 20010036101A1
• Time in Patent Office: 467 Days
• Field of Search: 365/145, 365/149
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.

Claims

1. A memory cell configuration, comprising:

a semiconductor substrate; and

a multiplicity of memory cells each having a selection transistor with a terminal, a memory transistor with a control electrode, and a ferroelectric capacitor disposed in an integrated manner in said semiconductor substrate, said selection transistor and said memory transistor connected in series through said terminal of said selection transistor, said ferroelectric capacitor connected between said terminal of said selection transistor and said control electrode of said memory transistor.

2. The memory cell configuration according to claim 1, including:

a word line, said selection transistor has a gate electrode connected to said word line, and said selection transistor and said memory transistor are MOS transistors;

a reference line; and

a bit line, said selection transistor and said memory transistor are connected in series between said bit line and said reference line.

3. The memory cell configuration according to claim 2, wherein said memory transistor has a terminal connected to said reference line, and including a resistor connected between said control electrode of said memory transistor and said reference line.

4. The memory cell configuration according to claim 3, wherein said ferroelectric capacitor has a first electrode, a ferroelectric layer and a second electrode, said ferroelectric layer contains a material selected from the group consisting of strontium bismuth tantalate, lead zirconium titanate, lithium niobate and barium strontium titanate.

5. The memory cell-configuration according to claim 1, wherein said memory transistor has a terminal and a source/drain region connected to said terminal of said memory transistor and overlapping said control electrode of said memory transistor.

6. The memory cell configuration according to claim 5, wherein said overlapping between said source/drain region and said control electrode of said memory transistor amounts to at least 10% of an area of said control electrode.

7. The memory cell configuration according to claim 1, wherein said ferroelectric capacitor and said control electrode of said memory transistor have substantially equivalent capacitances.