Combining RAM and ROM into a single memory array

• US 6,438,024 B1
• Filed: 01/11/2001
• Issued: 08/20/2002
• Est. Priority Date: 01/11/2001
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Lamere, Marc, Gold, Spencer M.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US09/758,492
• Publication Number:
  US 20020089873A1
• Time in Patent Office: 586 Days
• Field of Search: 365/203, 365/230.03, 365/154
• US Class Current: 365/154
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells

Abstract

A memory device that combines RAM and ROM devices into a single memory array is provided. The memory array includes a memory cell for the RAM that is associated with a first bit line and a first word line. The memory array also includes a second memory cell for the ROM that is associated with a second bit line and a second word line. The first bit line and the second bit line are connected with each other. The second memory cell is provided with a circuit that discharges the second bit line to represent a logical value “0” in response to a signal from the second word line.

Claims

1. A memory array, comprising:

a first memory cell for Random Access Memory (RAM) that is associated with a bit line and a word line;

a second memory cell for Read Only Memory (ROM) that is associated with the bit line and the word line; and

a circuit associated with the second memory cell for providing the bit line with a logical value in response to a signal from the word line, the circuit including a switching element connected between the bit line and ground and wherein the circuit is controlled by the signal from the word line.

2. The array of claim 1 wherein said first memory cell for the RAM is a static RAM (SRAM) cell.

3. The array of claim 1 wherein said first memory cell for the RAM is a dynamic RAM (DRAM) cell.

4. The array of claim 1 wherein said bit line is precharged before a read operation or a write operation.

5. The array of claim 4 wherein said array further includes means for preventing the line when precharged from discharging to represent a logical value “

1”

in response to a signal from the word line.

6. The array of claim 1 wherein said word line provided signals for selecting the first and second memory cells, said signals being produced by decoding signals for the addresses of the first and second memory cells.

7. A memory device, comprising:

a memory array that combines RAM cells and ROM cells into a single array, each said cell being associated with a word line and a bit line;

a precharger for precharging the bit lines of the memory cells before read operation of the cells; and

a decoder for decoding an address that corresponds to a row of the memory cell and generating a selection signal for selecting the row.

8. The device of claim 7 wherein said memory array includes at least a plurality of RAM cells grouped in a first orientation and a plurality of ROM cells grouped in a second orientation, said memory cells of a same orientation being connected to a same word line.

9. The device of claim 7 wherein said memory cells of a same column are connected to a same bit line.

10. The device of claim 7 wherein said ROM cell includes a switching element connected between the word line and the bit line to provide the bit line with a logical value in response to the signals from the word line.

11. The device of claim 10 wherein said switching element is a transistor and said transistor is pulled down to ground to provide a logical value ‘

0’

in response to the signals for selecting the ROM cell.

12. The device of claim 10 wherein said switching element is open ended to provide a logical value ‘

1’

in response to the signals for selecting the ROM cell.

13. A method for combining RAM cells and ROM cells into a memory device, said method comprising the steps of:

providing the RAM cells and ROM cells in a single array;

connecting the memory cells of a same first orientation to a same word line;

connecting the memory cells of a same second orientation to a same bit line;

providing a RAM cell with a logic circuit that provides a logical value to the bit line in response to signals from the word line, the logic circuit adapted to include a switching element connected between the bit line and the word line to provide a logical value “

0”

to the bit line in response to signals from the word line.

14. The method of claim 13 wherein said RAM cells include a static RAM (SRAM) cell.

15. The method of claim 13 wherein said RAM cells includes a dynamic RAM (DRAM) cell.

16. The method of claim 13 wherein said switching element is a transistor and wherein said transistor includes a gate connected to the word line, a source connected to the bit line and a drain connected to ground.

17. A microprocessor, comprising:

a memory array that combines RAM cells and ROM cells into a single memory array, each said memory cell being associated with a word line and a bit line;

a precharger for precharging the bit line of the memory cell before read or write operation of the cell; and

a decoder for decoding address signals of the memory cell to select a memory cell.

18. The device of claim 17 wherein said memory array includes at least RAM cells in a first orientation and ROM cells in a second orientation, the memory cells of a same orientation being connected to a same word line.

19. The device of claim 17 wherein said memory cells of a same column are connected to a same bit line.

20. The device of claim 17 wherein said ROM cell includes a switching element connected between the word line and the bit line to provide a logical value.

21. The device of claim 17 wherein said switching element is a transistor that is pulled down to ground to discharge the bit line to a logical value “

0.”