Semiconductor integrated circuit device, production and operation method thereof

• US 6,438,028 B1
• Filed: 07/13/2000
• Issued: 08/20/2002
• Est. Priority Date: 07/14/1999
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd. (Japan Display Incorporated)
• Inventors: Kobayashi, Takashi, Kume, Hitoshi, Kobayashi, Naoki, Kimura, Katsutaka, Kurata, Hideaki, Saeki, Shunichi
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/616,072
• Time in Patent Office: 768 Days
• Field of Search: 365/185.01, 365/185.06, 365/185.1, 365/185.17, 365/185.26, 365/185.05, 438/259, 438/260, 257/314, 257/315, 257/316, 257/320, 257/321
• US Class Current: 365/185.05
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.

Claims

1. A semiconductor integrated circuit device having a non-volatile memory, comprising:

a well of a first conductivity type formed on a main surface of a semiconductor substrate,

a plurality of semiconductor regions of a second conductivity type formed in said well and extending in a first direction and in parallel with one another,

a plurality of first gates formed over portions of said well located between said plurality of semiconductor regions through a first insulator film, and arranged in matrix,

a plurality of second gates each formed over at least some of said first gates arranged in identical lines through a second insulator film and extending in a second direction crossing said first direction, and

a plurality of third gates extending in said first direction, wherein;

a plurality of memory cells, each including one of said first gates, are electrically connected in parallel between adjoining pairs of said semiconductor regions, and each of said third gates is buried in a space between two of said first gates adjoining each other as viewed in said second direction in such a manner that an upper surface of said third gate is at a lower level than that of an upper surface of said first gate, and a third insulator film is formed between a side surface of each of said first gates and a side surface of each of said third gates.

2. A semiconductor integrated circuit device according to claim 1, wherein two of said first gates adjoining each other as viewed in said second direction are formed symmetrically with respect to one of said third gates located between said adjoining two first gates, and adjoining pairs of said third gates are formed symmetrically with respect to some of said first gates between said adjoining pairs of said third gates.

3. A semiconductor integrated circuit device according to claim 1, which has any one of the following constructions:

a first construction wherein said first gate is a floating gate, said second gate is a control gate and said third gate is an erase gate;

a second construction wherein said first gate is a floating gate, said second gate is a control gate and said third gate is a gate for controlling a split channel; and

a third construction wherein said first gate is a floating gate, said second gate is a control gate and said third gate is a gate having functions of both an erase gate and gate for controlling a split channel.

4. A semiconductor integrated circuit device according to claim 3, wherein a part of said third gate exists over said semiconductor region of the second conductivity type.

5. A semiconductor integrated circuit device according to claim 3, wherein said first gate is a floating gate, said second gate is a control gate and said third gate is an erase gate;

and

the entire surface of said third gate exists over said semiconductor region of the second conductivity type.

6. A semiconductor integrated circuit device according to claim 1, wherein said third insulator film is a silicon oxide film doped with nitrogen.