Dynamic memory circuit with automatic refresh function

• US 6,438,055 B1
• Filed: 10/17/2000
• Issued: 08/20/2002
• Est. Priority Date: 10/20/1999
• Status: Expired due to Fees

• Current Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Matsuzaki, Yasurou, Taguchi, Masao
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/688,941
• Time in Patent Office: 672 Days
• Field of Search: 365/222, 365/230.03, 365/230.06, 365/149
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

The present invention is that in a dynamic memory circuit, first and second internal operation cycles are assigned to one external operation cycle according to external commands, a memory core performs a read operation which corresponds to a read command at the first internal operation, and performs a refresh operation which responds to a refresh command at the second internal operation cycle. Also the memory core performs a refresh operation which responds to a refresh command at the first internal operation cycle, and performs a write operation which corresponds to a write command at the second internal operation cycle. It is preferable that when the read or write command is not input, the refresh operation is performed at the earlier internal operation cycle. And a refresh command generation circuit which generates the refresh command at a refresh time is created in the memory circuit.

Claims

1. A dynamic memory circuit which has volatile memory cells and performs a refresh operation at a predetermined timing, comprising:

a memory core having said memory cells; and

a refresh command generation circuit which generates a refresh command responding to a refresh signal generated at a predetermined timing, wherein

a first and second internal operation cycles are assigned to one external operation cycle according to the operation commands including a read command and a write command,

said memory core, responding to said read command, performs a read operation responding to said read command at said first internal operation cycle, and performs a refresh operation responding to said refresh command at said subsequent second internal operation cycle, and

said memory core, responding to said write command, performs a refresh operation responding to said refresh command at said first internal operation cycle, and performs a write operation at said second internal operation cycle.

2. The dynamic memory circuit according to claim 1, wherein when said read command or write command is not input, said memory core performs said refresh operation at the earlier cycle of said first or second internal operation cycle responding to said refresh command.

3. The dynamic memory circuit according to claim 1, wherein in said second internal operation cycle responding to said read command, said memory core performs said refresh operation when said refresh command is generated, and does not perform said refresh operation when said refresh command is not generated.

4. The dynamic memory circuit according to claim 1, further comprising an input/output terminal where data is input or output, wherein a plurality of bits of read data is output in serial from said input/output terminal after a read operation in said first internal operation cycle, and a write operation is performed at said second internal operation cycle for the plurality of bits of write data which is input in serial from said input/output terminal.

9. The dynamic memory circuit according to one of claim 1 to claim 8, wherein said memory core further comprises word lines, bit lines crossing said word lines, a sense amplifier to be connected to said bit lines, and said memory cells in association to said word lines and bit lines, and said memory core activates said word line and sense amplifier then precharges said bit lines within said internal operation cycle, responding to said operation command.

5. A dynamic memory circuit which has volatile memory cells and performs a refresh operation at a predetermined timing, comprising:

a memory core having a plurality of memory blocks including said memory cells; and

a refresh command generation circuit which generates a refresh command responding to a refresh signal generated at a predetermined timing, wherein

a plurality of internal operation cycles are assigned to one external operation cycle according to an operation command,

said memory core, responding to the operation command, performs an internal operation corresponding to said operation command in said plurality of memory blocks at each one of said internal operation cycles respectively, and performs said refresh operation corresponding to said refresh command in said memory blocks at an internal operation cycle where a corresponding internal operation is not performed.

6. The dynamic memory circuit according to claim 5, wherein

the first memory block of said plurality of memory blocks performs the internal operation corresponding to the operation command at the first internal operation cycle, and performs the refresh operation corresponding to said refresh command at the second internal operation cycle,

and the second memory block of said plurality of memory block performs the internal operation corresponding to the operation command at said second internal operation cycle, and performs the refresh operation corresponding to said refresh command at said first internal operation cycle.

7. A dynamic memory circuit which has volatile memory cells and performs a refresh operation at a predetermined timing, comprising:

a memory core having a first and second memory blocks which include said memory cells respectively; and

a refresh command generation circuit which generates a refresh command responding to a refresh signal generated at a predetermined timing, wherein

2N (N is an integer of 1 or more) internal operation cycles are assigned to one external operation cycle according to an operation command,

said memory core, responding to the operation command, performs an internal operation corresponding to said operation commands of first and second memory blocks at each one of said 2N internal operation cycles respectively, and performs a refresh operation corresponding to said refresh command in said memory blocks at an internal operation cycle where a corresponding internal operation is not performed.

8. A dynamic memory circuit which has volatile memory cells and performs a refresh operation at a predetermined timing, comprising:

a memory core which has 2M (M is an integer of 1 or more) memory blocks including said memory cells respectively; and

a refresh command generation circuit which generates a refresh command responding to a refresh signal generated at a predetermined timing, wherein

2N (N is an integer of 1 or more) internal operation cycles are assigned to one external operation cycle according to an operation command,

said memory core, responding to the operation command, performs an internal operation corresponding to said operation command of said memory blocks respectively at each one of said 2N internal operation cycles, and performs refresh operation corresponding to said refresh command in said memory blocks at an internal operation cycle where a corresponding operation is not performed.