DRAM refresh timing adjustment device, system and method

• US 6,438,057 B1
• Filed: 07/06/2001
• Issued: 08/20/2002
• Est. Priority Date: 07/06/2001
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Ruckerbauer, Hermann
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/900,626
• Time in Patent Office: 410 Days
• Field of Search: 365/222, 365/211, 365/228
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

An apparatus includes at least one dynamic random access memory (DRAM) array; and at least one temperature sensor in thermal communication with the DRAM array and operable to produce a signal indicative of a temperature of the DRAM array.

Claims

1. An apparatus, comprising:

a semiconductor package including at least one connection pin;

at least one dynamic random access memory (DRAM) array disposed within the package; and

at least one temperature sensor in thermal communication with the DRAM array, operable to produce a signal indicative of a temperature of the DRAM array, and coupled to the at least one connection pin such that the signal may be provided to external circuitry,

wherein the DRAM array is refreshed at a rate that decreases as the temperature of the DRAM array decreases and that increases as the temperature of the DRAM array increases.

2. The apparatus of claim 1, wherein the at least one temperature sensor includes at least one diode having a forward voltage drop that varies as a function of the temperature of the DRAM array, and the signal corresponds to the forward voltage drop of the at least one diode.

3. The apparatus of claim 1, wherein the at least one temperature sensor is taken from the group consisting of thermocouples and thermistors.

4. The apparatus of claim 1, wherein the at least one temperature sensor includes a diode having a forward voltage drop that varies as a function of the temperature of the DRAM array;

the at least one connection pin includes a first pin coupled to an anode of the diode and a second pin coupled to a cathode of the diode; and

the signal corresponds to a potential voltage between the first and second pins.

5. The apparatus of claim 1, wherein the at least one temperature sensor is taken from the group consisting of thermocouples and thermistors.

6. The apparatus of claim 1, further comprising a refresh unit operable to refresh the DRAM array at a rate that varies in response to the signal.

7. The apparatus of claim 6, wherein the refresh unit includes a refresh timing unit operable to establish the rate at which the DRAM array is refreshed in response to the signal.

8. The apparatus of claim 7, wherein the refresh timing unit is operable to decrease the rate at which the DRAM array is refreshed as the signal indicates that the temperature of the DRAM array decreases.

9. The apparatus of claim 7, wherein the refresh timing unit is operable to increase the rate at which the DRAM array is refreshed as the signal indicates that the temperature of the DRAM array increases.

10. The apparatus of claim 7, wherein the at least one temperature sensor includes at least one diode having a forward voltage drop that varies as a function of the temperature of the DRAM array, and the signal corresponds to the forward voltage drop of the at least one diode.

11. The apparatus of claim 10, wherein the refresh unit is operable to sense the forward voltage drop of the diode to determine the temperature of the DRAM array.

12. The apparatus of claim 6, wherein the DRAM array, the at least one temperature sensor, and the refresh unit are integrated in a semiconductor package.

13. A dynamic random access memory (DRAM) chipset, comprising:

at least one DRAM chip including a DRAM array and at least one temperature sensor in thermal communication with the DRAM array, the at least one temperature sensor being operable to produce a signal indicative of a temperature of the DRAM array, the DRAM chip including at least one connection pin operable to provide the signal to external circuitry; and

at least one refresh chip operable to refresh the DRAM array at a rate that varies in response to the signal, wherein the refresh chip is operable to (i) decrease the rate at which the DRAM array is refreshed as the signal indicates that the temperature of the DRAM array decreases; and

(ii) increase the rate at which the DRAM array is refreshed as the signal indicates that the temperature of the DRAM array increases.

14. The apparatus of claim 13, wherein the at least one temperature sensor includes at least one diode having a forward voltage drop that varies as a function of the temperature of the DRAM array, and the signal corresponds to the forward voltage drop of the at least one diode.

15. The apparatus of claim 14, wherein the refresh chip is operable to sense the forward voltage drop of the diode to determine the temperature of the DRAM array.

16. A method, comprising:

sensing a temperature of a dynamic random access memory (DRAM) array;

outputting a signal indicative of the temperature of the DRAM array to external circuitry; and

refreshing contents of the DRAM array at a rate that (i) decreases as the temperature of the DRAM array decreases; and

(ii) increases as the temperature of the DRAM array increase.

17. The method of claim 16, wherein the step of sensing the temperature of the DRAM array includes sensing a forward voltage drop of a diode that is in thermal communication with the DRAM array.