Method and circuit for sampling a signal at high sampling frequency

• US 6,438,366 B1
• Filed: 05/21/1999
• Issued: 08/20/2002
• Est. Priority Date: 05/29/1998
• Status: Expired due to Term

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Nokia Mobile Phones UK Limited (Nokia Corporation)
• Inventors: Halonen, Kari, Parssinen, Aarno, Lindfors, Saska
• Primary Examiner(s): TRAN, PABLO N
• Application Number:
  US09/316,357
• Publication Number:
  US 20020098823A1
• Time in Patent Office: 1,187 Days
• Field of Search: 455/334, 455/130, 455/295-299, 455/304, 455/311, 455/312, 455/337, 375/350, 375/319, 375/286, 330/259, 330/258, 330/311, 337/91, 337/95, 337/96, 341/143, 341/155, 341/118, 364/825, 364/724, 364/807, 364/829, 333/165-167
• US Class Current: 455/334
• CPC Class Codes: H03H 17/0291 Digital and sampled data filters
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

Electrical circuit (300, 500, 800, 900) has an input (301, 501, 801, 802, 901, 902) and an output (311, 502, OUT, I-OUT, Q-OUT). The circuit samples an input signal coupled to the input having a certain input frequency and converts the input signal into a certain output frequency at the output, the output frequency being lower than the input frequency. It comprises

a first sampler circuit (302, 510, 803, 910) coupled to the input,

a second sampler circuit (303, 520, 804, 920) coupled to the input,

a buffering component (309, 509, 809, 903, 904) coupled to the output and

buffer switching means (305-307, 514, 515, 811-818, 914, 915, 924, 925, 934, 935, 944, 945, 954, 955, 964, 965, 974, 975, 984, 985).

The buffer switching means are arranged to respond to a buffering command (f_s/N, A, B) by coupling said first sampler circuit and said second sampler circuit to said buffering component.

Claims

1. Electrical circuit for sampling an input signal having a certain input frequency and converting the input signal into a certain output frequency, the output frequency being lower than the input frequency, comprising

an input and an output,

a first sampler circuit coupled to the input,

a second sampler circuit coupled to the input,

a buffering component coupled to the output and

buffer switching means between said first and second sampler circuits and said buffering component;

wherein said buffer switching means are arranged to respond to a buffering command by coupling said first sampler circuit and said second sampler circuit to said buffering component.

2. Electrical circuit according to claim 1, comprising N sampler circuits coupled to the input, N being a positive integer greater than 2, whereby said buffer switching means are arranged to respond to said buffering command by coupling said N sampler circuits to said buffering component.

3. Electrical circuit according to claim 1 adapted for continuous sampling of the input signal by sampler circuits coupled to the input and comprising

a first sampling group consisting of a predetermined number of sampler circuits coupled to the input,

a second sampling group consisting of a predetermined number of sampler circuits coupled to the input,

first buffer switching means arranged to respond to a first buffering command by coupling the sampler circuits of said first sampling group to said buffering component and

second buffer switching means arranged to respond to a second buffering command by coupling the sampler circuits of said second sampling group to said buffering component.

4. Electrical circuit according to claim 1, wherein each sampler circuit comprises

a sampler input, a sampler output, a sampling command input and a buffering command input,

a sampling capacitance arranged to store a sample from a signal coupled to said sampler input and to provide a stored sample to the sampler output and

switching means arranged to respond to sampling commands brought into said sampling command input and buffering commands brought into said buffering command input and having a first state, a second state and a third state, of which

said first state corresponds to a tracking mode of the sampler wherein a sample is taken from a signal coupled to said sampler input and

said second state corresponds to a hold mode of the sampler wherein a sample taken in said first state is stored in the sampler and

said third state corresponds to an output mode of the sampler wherein a stored sample is provided to said sampler output.

5. Electrical circuit according to claim 1, wherein each sampler circuit comprises

a differential sampler input consisting of a first input line and a second input line,

a differential sampler output consisting of a first output line and a second output line,

a sampling command input,

a first sampling capacitance and a second sampling capacitance arranged to store a differential sample from a signal coupled to said sampler input and to provide a stored differential sample to the sampler output and

sampler switching means arranged to respond to sampling commands brought into said sampling command input and having a first state and a second state, of which

said first state corresponds to a tracking mode of the sampler wherein a differential sample is taken from a signal coupled to said sampler input and

said second state corresponds to a hold mode of the sampler wherein a stored differential sample is provided to said sampler output.

6. Electrical circuit according to claim 5, additionally comprising

a differential circuit input consisting of a first input line and a second input line,

means for coupling the first input line of each differential sampler input to the first input line of said differential circuit input,

means for coupling the second input line of each differential sampler input to the second input line of said differential circuit input,

a differential buffering component with a first input line and a second input line, and

within said buffer switching means, means arranged to respond to a buffering command by

coupling the first output line of the differential sampler output of the first sampler circuit to the first input line of said differential buffering component and the second output line of the differential sampler output of the first sampler circuit to the second input line of said differential buffering component and

coupling the first output line of the differential sampler output of the second sampler circuit to the second input line of said differential buffering component and the second output line of the differential sampler output of the second sampler circuit to the first input line of said differential buffering component.

7. Electrical circuit according to claim 5, additionally comprising

a differential circuit input consisting of a first input line and a second input line,

in an I-branch sampler group, a first sampler circuit and a second sampler circuit,

in a Q-branch sampler group, a third sampler circuit and a fourth sampler circuit,

means for coupling the first input line of each differential sampler input to the first input line of said differential circuit input,

means for coupling the second input line of each differential sampler input to the second input line of said differential circuit input,

an I-branch differential buffering component with a first input line and a second input line,

a Q-branch differential buffering component with a first input line and a second input line, and

within said buffer switching means,

means arranged to respond to a first buffering command by coupling the first output line of the differential sampler output of the first sampler circuit to the first input line of said I-branch differential buffering component, coupling the second output line of the differential sampler output of the first sampler circuit to the second input line of said I-branch differential buffering component, coupling the first output line of the differential sampler output of the third sampler circuit to the first input line of said Q-branch differential buffering component and coupling the second output line of the differential sampler output of the third sampler circuit to the second input line of said Q-branch differential buffering component and

means arranged to respond to a second buffering command by coupling the first output line of the differential sampler output of the second sampler circuit to the second input line of said I-branch differential buffering component, coupling the second output line of the differential sampler output of the second sampler circuit to the first input line of said I-branch differential buffering component, coupling the first output line of the differential sampler output of the fourth sampler circuit to the second input line of said Q-branch differential buffering component and coupling the second output line of the differential sampler output of the fourth sampler circuit to the first input line of said Q-branch differential buffering component.

8. Receiver for receiving radio frequency signals, comprising

a sampling downconverter block for implementing the downconversion of the received signals from a first frequency to a second frequency which is lower than the first frequency,

within the sampling downconverter block a first sampler circuit coupled to the input of the sampling downconverter block,

also within the sampling downconverter block a second sampler circuit coupled to the input of the sampling downconverter block,

also within the sampling downconverter block a buffering component coupled to the output of the sampling downconverter block and

also within the sampling downconverter block buffer switching means arranged to respond to a buffering command by coupling said first sampler circuit and said second sampler circuit to said buffering component.

9. Receiver according to claim 8, comprising a radio frequency part and a baseband part, wherein the sampling downconverter block is located between the radio frequency part and the baseband part for converting the received signals from radio frequency to baseband frequency.

10. Receiver according to claim 8, comprising a radio frequency part, an intermediate frequency part and a baseband part, wherein the sampling downconverter block is located between the intermediate frequency part and the baseband part for converting the received signals from an intermediate frequency to baseband frequency.

11. Method for sampling an input signal having a certain input frequency and converting the input signal into a certain output frequency, the output frequency being lower than the input frequency, comprising the steps of

taking a first sample from the input signal during a first sampling time interval and holding said first sample,

taking a second sample from the input signal during a second sampling time interval, which is later in time than said first sampling time interval, and holding said second sample,

taking a predetermined combination of said held first sample and said held second sample and

buffering said predetermined combination in an output buffer.

12. Method according to claim 11, comprising a repeatedly performed sampling cycle, wherein

during each sampling cycle N consecutive samples are taken from the input signal and held separately, where N is a positive integer greater than 2, and further during each sampling cycle a predetermined combination of said N consecutive samples is taken, and

said predetermined combination is buffered in an output buffer for the duration of the next sampling cycle.

13. Method according to claim 11, comprising a repeatedly performed sampling cycle consisting of a first part and a second part, wherein

during the first part of each sampling cycle N consecutive samples are taken from the input signal and held separately, where N is a positive integer,

during the second part of each sampling cycle M consecutive samples are taken from the input signal and held separately, where M is a positive integer,

during the first part of each sampling cycle a predetermined combination of the M consecutive samples taken during the second part of the previous sampling cycle is taken and buffered in an output buffer and

during the second part of each sampling cycle a predetermined combination of the N consecutive samples taken during the first part of the same sampling cycle is taken and buffered in an output buffer.

14. Method according to claim 11, wherein before taking said predetermined combination of said held first sample and said held second sample, said second sample is inverted.

15. Method according to claim 11, comprising a repeatedly performed sampling cycle consisting of a first part and a second part, wherein during said first part it comprises said steps of taking a first sample and a second sample and additionally the steps of

taking a third sample from the input signal during a third sampling time interval, which is later in time than said second sampling time interval, and inverting and holding said third sample,

taking a fourth sample from the input signal during a fourth sampling time interval, which is later in time than said third sampling time interval, and inverting and holding said fourth sample,

and during said second part it comprises said steps of

taking a fifth sample from the input signal during a fifth sampling time interval, which is later in time than said fourth sampling time interval, and holding said fifth sample,

taking a sixth sample from the input signal during a sixth sampling time interval, which is later in time than said fifth sampling time interval, and holding said sixth sample,

taking a seventh sample from the input signal during a seventh sampling time interval, which is later in time than said sixth sampling time interval, and inverting and holding said seventh sample, and

taking an eighth sample from the input signal during an eighth sampling time interval, which is later in time than said seventh sampling time interval, and inverting and holding said eighth sample,

and during the first part of each sampling cycle it additionally comprises the steps of

taking a predetermined combination of the fifth sample and inverted seventh sample taken during the second part of the previous sampling cycle and buffering said predetermined combination in a first output buffer and

taking the a predetermined combination of the sixth sample and inverted eighth sample taken during the second part of the previous sampling cycle and buffering said predetermined combination in a second output buffer,

and during the second part of each sampling cycle it additionally comprises the steps of

taking a predetermined combination of the first sample and inverted third sample taken during the first part of the same sampling cycle and buffering said predetermined combination in a first output buffer and

taking a predetermined combination of the second sample and inverted fourth sample taken during the first part of the same sampling cycle and buffering said predetermined combination in a second output buffer.

16. Method according to claim 15, wherein the input frequency is an intermediate frequency in a receiver, the sampling frequency corresponding to the taking of said first, third, fifth and seventh samples is the same as the sampling frequency corresponding to the taking of said second, fourth, sixth and eighth samples, which is four times said intermediate frequency, and the frequency of buffering the predetermined combinations of said samples is the same as said intermediate frequency.

17. Electrical circuit for sampling an input signal having a certain input frequency and converting the input signal into a certain output frequency, the output frequency being lower than the input frequency, comprising:

an input and an output;

a first sampler circuit coupled to the input;

a second sampler circuit coupled to the input;

a buffering component coupled to the output; and

buffer switching means between said first and second sampler circuits and said buffering component;

wherein said buffer switching means are arranged to respond to a buffering command by coupling said first sampler circuit and said second sampler circuit to said buffering component;

and wherein each sampler circuit comprises;

a differential sampler input consisting of a first input line and a second input line,

a differential sampler output consisting of a first output line and a second output line;

a sampling command input;

a first sampling capacitance and a second sampling capacitance arranged to store a differential sample from a signal coupled to said sampler input and to provide a stored differential sample to the sampler output, and

sampler switching means arranged to respond to sampling commands brought into said sampling command input and having a first state and a second state, of which said first state corresponds to a tracking mode of the sampler wherein a differential sample is taken from a signal coupled to said sampler input and said second state corresponds to a hold mode of the sampler wherein a stored differential sample is provided to said sampler output.

18. Electrical circuit according to claim 17, additionally comprising a differential circuit input consisting of a first input line and a second input line;

means for coupling the first input line of each differential sampler input to the first input line of said differential circuit input;

means for coupling the second input line of each differential sampler input to the second input line of said differential circuit input,

a differential buffering component with a first input and a second input line, and

within said buffer switching means, means arranged to respond to a buffering command by

coupling the first output line of the differential sampler output of the first sampler circuit to the first input line of said differential buffering component and the second output line of the differential sampler output of the first sampler circuit to the second input line of said differential buffering component, and

coupling the first output line of the differential sampler output of the second sampler circuit to the second input line of said differential buffering component and the second output line of the differential sampler output of the second sampler circuit to the first input line of said differential buffering component.

19. Electrical circuit according to claim 17, additionally comprising:

a differential circuit input consisting of a first input line and a second input line,

in an I-branch sampler group, a first sampler circuit and a second sampler circuit,

in a Q-branch sampler group, a third sampler circuit and a fourth sampler circuit,

means for coupling the first input line of each differential sampler input to the first input line of said differential circuit input,

means for coupling the second input line of each differential sampler input to the second input line of said differential circuit input,

an I-branch differential buffering component with a first input line and a second input line,

a Q-branch differential buffering component with a first input line and a second input line, and

within said buffer switching means,

means arranged to respond to a first buffering command by coupling the first output line of the differential sampler output of the first sampler circuit to the first input line of said I-branch differential buffering component, coupling the second output line of the differential sampler output of the first sampler circuit to the second input line of said I-branch differential buffering component, coupling the first output line of the differential sampler output of the third sampler circuit to the first input line of said Q-branch differential buffering component and coupling the second output line of the differential sampler output of the third sampler circuit to the second input line of said Q-branch differential buffering component, and

means arranged to respond to a second buffering command by coupling the first output line of the differential sampler output of the second sampler circuit to the second input line of said I-branch differential buffering component, coupling the second output line of the differential sampler output of the second sampler circuit to the first input line of said I-branch differential buffering component, coupling the first output line of the differential sampler output of the fourth sampler circuit to the second input line of said Q-branch differential buffering component and coupling the second output line of the differential sampler output of the fourth sampler circuit to the first input line of said Q-branch differential buffering component.

20. Method for sampling an input signal having a certain input frequency and converting the input signal into a certain output frequency, the output frequency being lower than the input frequency, comprising the steps of:

taking a first sample from the input signal during a first sampling time interval and holding said first sample,

taking a second sample from the input signal during a second sampling time interval, which is later in time than said first sampling time interval, and holding said second sample,

taking a predetermined combination of said held first sample and said held second sample, and

buffering said predetermined combination in an output buffer,

a repeatedly performed sampling cycle consisting of a first part and a second part, wherein during said first part it comprises said steps of taking a first sample and a second sample and additionally the steps of

taking a third sample from the input signal during a third sampling time interval, which is later in time than said second sampling time interval, and inverting and holding said third sample,

taking a fourth sample from the input signal during a fourth sampling time interval, which is later in time than said third sampling time interval, and inverting and holding said fourth sample,

and during said second part it comprises said steps of

taking a fifth sample from the input signal during a fifth sampling time interval, which is later in time than said fourth sampling time interval, and holding said fifth sample,

taking a sixth sample from the input signal during a sixth sampling time interval, which is later in time than said fifth sampling time interval, and holding said sixth sample,

taking a seventh sample from the input signal during a seventh sampling time interval, which is later in time than said sixth sampling time interval, and inverting and holding said seventh sample, and

taking an eighth sample from the input signal during an eighth sampling time interval, which is later in time than said seventh sampling time interval, and inverting and holding said eighth sample,

and during the first part of each sampling cycle it additionally comprises the steps of taking a predetermined combination of the fifth sample and inverted seventh sample taken during the second part of the previous sampling cycle and buffering said predetermined combination in a first output buffer, and

taking a predetermined combination of the sixth sample and inverted eighth sample taken during the second part of the previous sampling cycle and buffering said predetermined combination in a second output buffer,

and during the second part of each sampling cycle it additionally comprises the steps of;

taking a predetermined combination of the first sample and inverted third sample taken during the first part of the same sampling cycle and buffering said predetermined combination in a first output buffer; and

taking a predetermined combination of the second sample and inverted fourth sample taken during the first part of the same sampling cycle and buffering said predetermined combination in a second output buffer.

21. Method according to claim 20, wherein the input frequency is an intermediate frequency in a receiver, the sampling frequency corresponding to the taking of said first, third, fifth and seventh samples is the same as the sampling frequency corresponding to the taking of said second, fourth, sixth and eighth samples, which is four times said intermediate frequency, and the frequency of buffering the predetermined combinations of said samples is the same as said intermediate frequency.