Power dissipation reduction in medical devices using adiabatic logic

• US 6,438,422 B1
• Filed: 12/20/1999
• Issued: 08/20/2002
• Est. Priority Date: 10/28/1998
• Status: Expired due to Fees

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Schu, Carl A., Greeninger, Daniel R., Thompson, David L.
• Primary Examiner(s): EVANISKO, GEORGE ROBERT
• Application Number:
  US09/467,288
• Time in Patent Office: 974 Days
• Field of Search: 607/1, 607/2, 607/4, 607/5, 607/9, 607/16
• US Class Current: 607/16
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/3605 Implantable neurostimulators for stimulating central or peripheral nerve system
• CPC Class Codes: A61N 1/378 Electrical supply
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03K 19/0019 by energy recovery or adiabatic operation
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system for minimizing power dissipation within an implantable medical device through use of adiabatic logic is disclosed. The system includes a first and a second sub-circuit of the implantable medical device. An electrical connection interconnects the first and the second sub-circuits, the electrical connection including a capacitive element. Circuitry, which charges the capacitive element of the electrical connection to generate a ramp logic signal, is connected to the capacitive element. The ramp logic signal includes a frequency of less than 500 kilohertz, thereby creating a low frequency, low power system which reduces energy dissipation to the surrounding environment.

Claims

1. An implantable medical device system having a bus and first and second logic electrical components, said bus extending between said components, said system for generating a logic signal and for minimizing power dissipation within the implantable medical device, the system comprising:

means for defining a first potential;

a capacitive element associated with the bus and the first potential;

N voltage supplies, wherein N>

1;

N switches corresponding to the N voltage supplies, each switch being operatively coupled between a corresponding one of the N voltage supplies and the capacitive element;

a first switch operatively coupled in parallel with the capacitive element between the N switches and the first potential; and

a controller operatively coupled to the N switches and to the first switch to control the N switches to generate a ramped logic signal across the capacitive element that is applied to the bus and to either logic electrical component and to control the first switch to reset the voltage on the capacitor to the first potential.

2. The system of claim 1, wherein the capacitive element includes an internal capacitance within the bus between the first electrical component and the second electrical component of the implantable medical device.

3. The system of claim 2, wherein the logic signal generated across the capacitive element is provided to the first electrical component.

4. The system of claim 2, wherein the logic signal generated across the capacitive element is provided to the second electrical component.

5. The system of claim 1, wherein the logic signal generated across the capacitive element operates at a frequency of less than 500 kilohertz.

6. The system of claim 1, wherein the controller is operable to open the first switch and to selectively close the N switches in a timed sequence to charge the capacitive element from the first potential through N voltage steps, thereby providing a ramped leading edge of the logic signal.

7. The system of claim 6, wherein the controller is operable to selectively open the N switches in a timed sequence and to close the first switch after all of the N switches are opened to discharge the capacitive element to the first potential, thereby providing a ramped trailing edge of the logic signal.