Cache memory control circuit including summarized cache tag memory summarizing cache tag information in parallel processor system

• US 6,438,653 B1
• Filed: 06/14/1999
• Issued: 08/20/2002
• Est. Priority Date: 06/16/1998
• Status: Expired due to Term

• Current Assignee: Maxell, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Okochi, Toshio, Kashiyama, Masamori, Akashi, Hideya, Shonai, Toru
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US09/330,981
• Time in Patent Office: 1,163 Days
• Field of Search: 711/122, 711/141, 711/119, 711/128, 711/154, 711/145, 711/118, 711/129, 711/144, 711/156
• US Class Current: 711/128
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing

Abstract

A multi-processor system includes a plurality of processor node control circuits in respective processor nodes, and a cache memory which is an external cache. Each of the processor node control circuits includes a summarized cache tag memory for storing “summarized information” which is information having a reduced number of bits by summarizing information on a cache tag portion in the cache memory and indicating whether each of blocks is effectively indexed in the cache tag portion. For cache coherence control, the summarized cache tag memory is first accessed, so that the cache tag portion is accessed only when it is determined that a target block is effectively indexed, to determine whether the cache coherence control for the node is required.

Claims

1. A cache memory control circuit for controlling a cache memory provided in a parallel computer system having a shared memory accessible from a plurality of processors, wherein said cache memory having a data portion for selectively storing data blocks of said shared memory and a cache tag portion having a plurality of sets of ways, each of the sets of ways including a plurality of ways each for registering tag information of a data block stored in said data portion, said cache memory controller circuit comprising:

a circuit for controlling said cache memory;

a summarized cache tag memory having a plurality of cache tag summarized information entries corresponding to the plurality of sets of ways of said cache tag portion; and

a cache tag summarized information control circuit for controlling said summarized cache tag memory,

wherein each of the cache tag summarized information entries possessed by said summarized cache tag memory has a bit length of N bits which is shorter than a total bit length required in each of the plurality of sets of ways of said cache tag portion for registering said tag information,

wherein addresses of datablocks likely to be stored in the plurality of sets of ways of said cache tag portion corresponding to said cache tag summarized information entries are classified into N groups,

wherein a first bit of each cache tag summarized information entry is registered as true when an effective address of a first group is stored in any way in said cache tag portion, and

wherein each of n-th bits of said cache tag summarized information entry is registered as true when an effective address of an n-th group is stored in any way in said cache tag portion, n being an integer from 2 to N.

2. The cache memory control circuit according to claim 1, further comprising:

an interface to one of said processor and an interface to another cache memory controller for controlling another cache memory provided in said parallel processor system,

wherein said cache tag summarized information control circuit reads a cache tag summarized information entry in said summarized cache tag memory in response to an access request from said interface to one of said processors or from said interface to another cache memory controller to determine whether or not a target block is likely to be stored in said cache tag portion,

wherein said cache tag summarized information control circuit determines that the target block is likely to be stored in said cache tag portion, when a bit corresponding to a group number of an address of the target block directed by said access request is true in said cache tag summarized information entry.

3. The cache memory control circuit according to claim 2, wherein when no access has been issued to said cache tag portion of said cache memory, said cache tag portion is accessed together with an access to said summarized cache tag memory, and

wherein when the access has been issued to said cache tag portion of said cache memory, the access to said summarized cache tag memory is only started.

4. The cache memory control circuit according to claim 1, wherein each block stored in said cache memory is managed in one of four statuses including an invalid status (“

Invalid”

), an exclusive status (“

Exclusive”

), a shared status (“

Shared”

) and a modified status (“

Modified”

) in said cache tag portion,

wherein said invalid status indicates that a target block is not stored in said cache memory,

wherein said exclusive status indicates that a target block is stored in said cache memory, the block stored in the cache data portion is identical to corresponding data on a memory, and said block is not stored in any other cache memory connected on the lower hierarchical side,

wherein said shared status indicates that a target block is stored in said cache memory, the block stored in the cache data portion is identical to corresponding data on a memory, and said block is likely to be stored in another cache memory connected to the lower hierarchical side,

wherein said modified status indicates that a target block is stored in said cache memory, the block stored in the cache data portion stores modified data different from corresponding data on a memory, and said block is not stored in any other cache memory connected on the lower hierarchical side, and

wherein contents of an entry are registered in a cache tag summarized information entry in said summarized cache tag memory only when said cache memory holds a block in the modified status or in the shared status.

5. A cache memory control circuit for controlling a cache memory provided in a parallel computer system having a shared memory accessible from a plurality of processors, wherein said cache memory having a data portion for selectively storing data blocks of said shared memory and a cache tag portion having a plurality of sets of ways, each of the sets of ways including a plurality of ways each for registering tag information of a data block stored in said data portion, said cache memory controller circuit comprising:

a circuit for controlling said cache memory;

a summarized cache tag memory having a plurality of cache tag summarized information entries corresponding to the plurality of sets of ways of said cache tag portion; and

a cache tag summarized information control circuit for controlling said summarized cache tag memory,

wherein each of the plurality of sets of ways in said cache tag portion includes N ways,

wherein addresses of blocks likely to be stored in the plurality of sets of ways of said cache tag portions are classified into M groups,

wherein each cache tag summarized information entry possessed by said summarized cache tag memory is composed of N fields,

wherein each of said fields includes a portion for storing a group number and a bit indicative of validity of said group number,

wherein when an address stored in a first way of said cache tag portion is valid, said bit indicative of validity of a first field in said cache tag summarized information entry is set to “

1,” and

a group number of said address is stored in said group number storing portion for registration,

wherein when an address stored in the first way of said cache tag portion is not valid, said bit indicative of validity of said first field in said cache tag summarized information entry is set to “

0”

,

wherein when an address stored in a second way of said cache tag portion is valid, said bit indicative of validity of a second field in said cache tag summarized information entry is set to “

1,” and

a group number of said address is stored in said group number storing portion for registration,

wherein when an address stored in the second way of said cache tag portion is not valid, said bit indicative of validity of said second field in said cache tag summarized information entry is set to “

0”

,

wherein when an address stored in an Nth way of said cache tag portion is valid, said bit indicative of validity of an Nth field in said cache tag summarized information entry is set to “

1,” and

a group number of said address is stored in said group number storing portion for registration, and

wherein when an address stored in the Nth way of said cache tag portion is not valid, said bit indicative of validity of said Nth field in said cache tag summarized information entry is set to “

0.”

6. The cache memory control circuit according to claim 5, further comprising:

an interface an interface to one of said processor and an interface to another cache memory controller for controlling another cache memory provided in said parallel processor system,

wherein said cache tag summarized information control circuit reads a cache tag summarized information entry in said summarized cache tag memory in response to an access request from said interface to one of said processor or from said interface to another cache memory controller to determine whether or not a target block is likely to be stored in said cache tag portion, and

wherein said cache tag summarized information control circuit determines that it is likely that the target block is stored in said cache tag portion, when a group number of the address of the target block directed by said access request is stored in any field of said cache tag summarized information entry and a valid bit in said field is set at “

1.”

7. A cache memory control circuit for controlling a cache memory provided in a parallel computer system having a shared memory accessible from a plurality of processors, wherein said cache memory having a data portion for selectively storing data blocks of said shared memory and a cache tag portion having a plurality of sets of ways, each of the sets of ways including a plurality of ways each for registering tag information of a data block stored in said data portion, said cache memory controller circuit comprising:

a circuit for controlling said cache memory;

a summarized cache tag memory having a plurality of cache tag summarized information entries corresponding to the plurality of sets of ways of said cache tag portion; and

a cache tag summarized information control circuit for controlling said summarized cache tag memory,

wherein each of the plurality of sets of ways in said cache tag portion includes N ways,

wherein addresses of blocks likely to be stored in the plurality of sets of ways of said cache tag portion are classified into N groups,

wherein each cache tag summarized information entry possessed by said summarized cache tag memory is composed of N fields for storing group numbers,

wherein when an address stored in a first way of said cache tag portion is valid, a first field of said cache tag summarized information entry stores a group number of said address for registration,

wherein when an address stored in a second way of said cache tag portion is valid, a second field of said cache tag summarized information entry stores a group number of said address for registration, and

wherein when an address stored in an Nth field of said cache tag portion is valid, an Nth field of said cache tag summarized information entry stores a group number of said address for registration.

8. The cache memory control circuit according to claim 7, further comprising:

an interface to one of said processors and an interface to another cache memory controller for controlling another cache memory provided in said parallel processor system,

wherein said cache tag summarized information control circuit reads a cache tag summarized information entry in said summarized cache tag memory in response to an access request from said interface to one of said processors or from said interface to another cache memory controller to determine whether or not a target block is likely to be stored in said cache tag portion,

wherein said cache tag summarized information control circuit determines that the target block is likely to be stored in said cache tag portion, when a group number of the address of the target block directed by said access request is stored in any field of said cache tag summarized information entry.