Directory based cache coherency system supporting multiple instruction processor and input/output caches

• US 6,438,659 B1
• Filed: 08/24/2000
• Issued: 08/20/2002
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Bauman, Mitchell A., Rodi, Eugene A., Morrissey, Douglas E.
• Primary Examiner(s): Kim, Matthew
• Assistant Examiner(s): Vital, Pierre M.
• Application Number:
  US09/645,233
• Time in Patent Office: 726 Days
• Field of Search: 711/141, 711/118, 711/119, 711/144, 711/146, 711/145, 711/154, 711/152, 711/148, 711/149, 711/156, 711/206, 711/207, 711/208, 710/39, 710/132, 710/21, 710/5
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0886 Variable-length word access
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/0) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.

Claims

1. For use in a data processing system having multiple instruction processors (IPs) and multiple input/output (I/O) systems, a memory system, comprising:

a shared main memory to store addressable blocks of data signals;

one or more IP caches each coupled to one or more of the IPs and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;

one or more I/O memories each coupled to an associated one or more of the I/O systems and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;

a directory storage device coupled to said shared main memory to store directory information for each associated one of said addressable blocks, said directory information indicating which of said one or more IP caches and which of said one or more I/O memories is storing an associated addressable block of data signals, said directory information further including access privilege indicators for said associated addressable block of data signals, said access privilege indicators being selected from a first set of access privilege indicators if at least one of said IP caches stores said associated addressable block, said access privilege indicators being selected from a second set of access privilege indicators if only said one or more I/O memories stores said associated addressable block,

wherein each of said IP caches and each of said I/O memories includes circuits to issue commands to said shared main memory, each of said commands to request a copy of a requested one of said addressable blocks of data signals,

and further including a control circuit coupled to ones of said IP caches and ones of said I/O memories to receive said issued commands, and to determine, based on a selected one of said issued commands for said requested one of the addressable blocks of data signals, and further based on said associated one of said access privilege indicators for said requested one of said addressable blocks of data signals, which one of said access privilege indicators is to be associated with said requested one of said addressable blocks of data signals upon completion of execution of said selected one of said issued command, and

wherein each of said IP caches and ones of said I/O memories may return modified said requested ones of said addressable blocks of data signals to said shared main memory to be stored during return operations, and wherein said directory storage device includes an error circuit responsive to said return operations such that any of said return operations causes an error signal to be issued if said return operation is performed by any of said IP caches or any of said I/O memories not indicated by said directory information as storing any one of said modified requested ones of said addressable blocks of data signals.

2. The memory system of claim 1, wherein ones of said access privilege indicators indicate exclusive cache states such that any of said requested addressable blocks associated with said exclusive cache states may be stored within at most one of said IP caches or one of said I/O memories at any given time.

3. The memory system of claim 2 wherein if a requesting one of said IP caches or a requesting one of said I/O memories makes a request to said shared main memory for a requested one of said addressable blocks of data signals associated with one of said exclusive cache states, and said requested one of said addressable blocks of data signals is stored within a storing one of said IP caches, said control unit causes said storing one of said IP caches to provide said requested one of said addressable blocks of data signals to said shared main memory, and further causes said requested one of said addressable blocks of data signals to be associated with a different said cache state.

4. The memory system of claim 2 wherein if a requesting one of said IP caches or said I/O memories makes a request to said shared main memory for a requested one of said addressable blocks of data signals associated with one of said exclusive cache states, and said requested one of said addressable blocks of data signals is stored within a storing one of said I/O memories, said shared main memory allows said storing one of said I/O memories to retain said requested one of said addressable blocks of data signals, which is maintained in said one of said exclusive cache states.

5. For use in a data processing system having multiple instruction processors (IPs) and multiple input/output (I/O) systems, a memory system, comprising:

a shared main memory to store addressable blocks of data signals;

one or more IP caches each coupled to one or more of the IPs and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;

one or more I/O memories each coupled to an associated one or more of the I/O systems and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;

a directory storage device coupled to said shared main memory to store directory information for each associated one of said addressable blocks, said directory information indicating which of said one or more IP caches and which of said one or more I/O memories is storing an associated addressable block of data signals, said directory information further including access privilege indicators for said associated addressable block of data signals, said access privilege indicators being selected from a first set of access privilege indicators if at least one of said IP caches stores said associated addressable block, said access privilege indicators being selected from a second set of access privilege indicators if only said one or more I/O memories stores said associated addressable block,

and further including a control circuit to determine, based on said access privilege indicators for an associated addressable block of data signals, the number of said IP caches or the number of said I/O memories which may store said associated addressable block of data signals, and the manner in which said addressable block of data signals may be read from, or written to, within the memory system, and

wherein predetermined ones of the I/O memories are I/O caches, and wherein access privilege indicators are provided to allow ones of said addressable blocks of data signals to be stored by ones of said I/O caches to be used by said coupled ones of the I/O systems for read-only purposes.

6. For use in a data processing system having multiple instruction processors (IPs) and multiple input/output (I/O) systems, a memory system, comprising:

a shared main memory to store addressable blocks of data signals;

one or more IP caches each coupled to one or more of the IPs and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;

one or more I/O memories each coupled to an associated one or more of the I/O systems and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;

a directory storage device coupled to said shared main memory to store directory information for each associated one of said addressable blocks, said directory information indicating which of said one or more IP caches and which of said one or more I/O memories is storing an associated addressable block of data signals, said directory information further including access privilege indicators for said associated addressable block of data signals, said access privilege indicators being selected from a first set of access privilege indicators if at least one of said IP caches stores said associated addressable block, said access privilege indicators being selected from a second set of access privilege indicators if only said one or more I/O memories stores said associated addressable block,

and further including a control circuit to determine, based on said access privilege indicators for an associated addressable block of data signals, the number of said IP caches or the number of said I/O memories which may store said associated addressable block of data signals, and the manner in which said addressable block of data signals may be read from, or written to, within the memory system, and

wherein predetermined ones of the I/O memories are I/O buffers, and wherein access privilege indicators included within said second set of access privilege indicators are provided to allow associated ones of said addressable blocks of data signals each to be stored within any one of said I/O buffers, and whereby ones of the I/O systems may read from, or write to, said addressable blocks of data signals stored within said I/O buffers coupled to said ones of the I/O systems.

7. For use in a data processing system having multiple instruction processors (IPs) and multiple input/output (I/O) systems, a memory system, comprising:

a shared main memory to store addressable blocks of data signals;

one or more IP caches each coupled to one or more of the IPs and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;

one or more I/O memories each coupled to an associated one or more of the I/O systems and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;

a directory storage device coupled to said shared main memory to store directory information for each associated one of said addressable blocks, said directory information indicating which of said one or more IP caches and which of said one or more I/O memories is storing an associated addressable block of data signals, said directory information further including access privilege indicators for said associated addressable block of data signals, said access privilege indicators being selected from a first set of access privilege indicators if at least one of said IP caches stores said associated addressable block, said access privilege indicators being selected from a second set of access privilege indicators if only said one or more I/O memories stores said associated addressable block,

wherein each of said IP caches and each of said I/O memories includes circuits to issue commands to said shared main memory, each of said commands to request a copy of a requested one of said addressable blocks of data signals,

and further including a control circuit coupled to ones of said IP caches and ones of said I/O memories to receive said issued commands, and to determine, based on a selected one of said issued commands for said requested one of the addressable blocks of data signals, and further based on said associated one of said access privilege indicators for said requested one of said addressable blocks of data signals, which one of said access privilege indicators is to be associated with said requested one of said addressable blocks of data signals upon completion of execution of said selected one of said issued command, and

wherein one of said control circuit includes a circuit responsive to one of said commands that is a fetch MSU own command to cause requested one of said addressable blocks of data signals to become associated with predetermined ones of said access privilege indicators that indicate that said shared main memory is prepared to be partitioned into multiple systems.

8. For use in a data processing system having multiple instruction processors (IPs) and multiple input/output (I/O) systems, a memory system, comprising:

a shared main memory to store addressable blocks of data signals;

one or more IP caches each coupled to one or more of the IPs and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;

one or more I/O memories each coupled to an associated one or more of the I/O systems and each coupled to said shared main memory to store selectable ones of said addressable blocks of data signals received from said shared main memory;

a directory storage device coupled to said shared main memory to store directory information for each associated one of said addressable blocks, said directory information indicating which of said one or more IP caches and which of said one or more I/O memories is storing an associated addressable block of data signals,

wherein each of said IP caches and each of said I/O memories includes circuits to issue commands to said shared main memory, each of said commands to request a copy of a requested one of said addressable blocks of data signals,

and further including a control circuit coupled to ones of said IP caches and ones of said I/O memories to receive said issued commands, and to determine, based on a selected one of said issued commands for said requested one of the addressable blocks of data signals, and further based on said associated one of said access privilege indicators for said requested one of said addressable blocks of data signals, which one of said access privilege indicators is to be associated with said requested one of said addressable blocks of data signals upon completion of execution of said selected one of said issued command, and

wherein each of said IP caches and ones of said I/O memories may return modified said requested ones of said addressable blocks of data signals to said shared main memory to be stored during return operations, and wherein said directory storage device includes an error circuit responsive to said return operations such that any of said return operations causes an error signal to be issued if said return operation is performed by any of said IP caches or any of said I/O memories not indicated by said directory information as storing any one of said modified requested ones of said addressable blocks of data signals.