Generating partition corresponding real address in partitioned mode supporting system

• US 6,438,671 B1
• Filed: 07/01/1999
• Issued: 08/20/2002
• Est. Priority Date: 07/01/1999
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tsuchiya, Kenichi, Silha, Edward John, Doing, Richard William, Kalla, Ronald Nick, Schwinn, Stephen Joseph
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US09/346,206
• Time in Patent Office: 1,146 Days
• Field of Search: 711/173, 711/202, 712/229
• US Class Current: 711/173
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

A processor supports logical partitioning of a computer system. Logical partitions isolate the real address spaces of processes executing on different processors and the hardware resources that include processors. However, this multithreaded processor system can dynamically reallocate hardware resources including the processors among logical partitions. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not. In the preferred embodiment, instruction addresses from either active or dormant threads can be pre-fetched in anticipation of execution. In the preferred embodiment, the processor supports different environments which use the hypervisor, supervisor and problem states differently.

Claims

1. A computer processing apparatus for supporting a computer system divisible into a plurality of logical partitions, each partition having a respective portion of the real address space of said computer system, said computer processing apparatus comprising:

effective address generating logic, said effective address generating logic generating effective addresses to be accessed, wherein at least some of said effective addresses generated by said effective address generating logic are base real addresses;

at least one state register for recording processor operating parameters, said at least one state register including a mode designator, said mode designator designating an operating mode;

real address partitioning logic, said real address partitioning logic modifying one or more high order bits of said base real address to generate a partitioned real address when said base real address is associated with a first operating mode, said partitioned real address lying within the portion of the real address space of said computer system of a logical partition associated with said computer processing apparatus, and said real address partitioning logic not modifying said one or more high order bits of said base real address when said base real address is associated with a second operating mode.

2. The computer processing apparatus of claim 1, further comprising:

real address range checking logic, said real address range checking logic generating an error signal responsive to detecting a base real address outside a predetermined range when said base real address is associated with said first operating mode, and not generating an error signal responsive to detecting a base real address outside a predetermined range when said base real address is associated with said second operating mode.

3. The computer processing apparatus of claim 1,

wherein at least some of said effective addresses generated by said effective address generating logic are translatable addresses intended for translation from an effective address to a real address;

and

wherein said computer processing apparatus further comprises real address selection logic for selectively outputting a real address translated from said effective address when said effective address is a translatable address, and outputting a real address generated by said real address partitioning logic when said effective address is a base real address.

4. The computer processing apparatus of claim 3, further comprising:

an effective-to-real address translation table, wherein at least some of said effective addresses which are translatable addresses are translated from an effective address to a real address by reference to said effective-to-real address translation table.

5. The computer processing apparatus of claim 1, further comprising:

a plurality of sets of registers for supporting the execution of a plurality of threads, each set of registers corresponding to a respective one of said plurality of threads;

wherein said at least one state register for recording processor operating parameters comprises a respective mode designator associated with each thread, said mode designator designating, for each of said threads independently, a respective operating mode; and

wherein said real address partitioning logic modifies one or more high order bits of said base real address to generate a partitioned real address when said base real address is generated on behalf of a thread in said first operating mode, and does not modify said one or more high order bits of said base real address when said base real address is generated on behalf of a thread in said second operating mode.

6. The computer processing apparatus of claim 5, further comprising:

real address range checking logic, said real address range checking logic generating an error signal responsive to detecting a base real address outside a predetermined range when said base real address is generated on behalf of a thread in said first operating mode, and not generating an error signal responsive to detecting a base real address outside a predetermined range when said base real address is generated on behalf of a thread in said second operating mode.

7. The computer processing apparatus of claim 5, wherein said effective address generating logic comprises an instruction unit for generating effective addresses of instructions for execution by said computer processing apparatus, said instruction unit generating effective addresses on behalf of an active thread and on behalf of at least one dormant thread, said real address partitioning logic selectively modifying one or more high order bits of said base real address to generate a partitioned real address on behalf of an active thread and on behalf of at least one dormant thread responsive to said mode designator associated with the respective thread.

8. The computer processing apparatus of claim 5, wherein said mode designator is placed in said second operating mode only upon occurrence of one of a set of predefined events, each said predefined event of said set of predefined events causing said processing unit to branch to a respective predefined real memory address.

9. The computer processing apparatus of claim 8, wherein a state represented by said at least one state register is saved in a saved state register upon occurrence of one of said set of predefined events, and restored to said at least one state register upon return from processing said one of said set of predefined events.

10. The computer processing apparatus of claim 2, wherein said real address range checking logic further comprises:

a real memory limit register specifying a range of address bits of said effective address;

AND logic performing a plurality of logical ANDs of each of a plurality of address bits derived from said effective address generated by effective address generation logic with a respective bit from a mask generated from a value in said real memory limit register to produce a masked portion of said effective address; and

OR logic for performing a logical OR of a plurality of address bits derived from said effective address generated by said effective address generation logic, said plurality of address bits derived from said effective address including said masked portion of said effective address generated by said effective address generation logic.

11. The computer processing apparatus of claim 1, wherein said real address partitioning logic comprises:

a real memory offset register containing a plurality of address bits defining a logical address partition; and

OR logic performing a plurality of logical ORs of each of a plurality of address bits derived from said effective address generated by said effective address generating logic with a respective bit from said real memory offset register.

12. The computer processing apparatus of claim 1, wherein said mode designator is placed in said second operating mode only upon occurrence of one of a set of predefined events.

13. The computer processing apparatus of claim 12, wherein each said predefined event of said set of predefined events causes said processing unit to branch to a respective predefined real memory address.

14. The computer processing apparatus of claim 12, wherein a state represented by said at least one state register is saved in a saved state register upon occurrence of one of said set of predefined events, and restored to said at least one state register upon return from processing said one of said set of predefined events.

15. A computer processing apparatus for supporting a computer system divisible into a plurality of logical partitions, each partition having a respective portion of the real address space of said computer system, said computer processing apparatus comprising:

means for maintaining state information for at least one thread;

means for generating effective addresses for said at least one thread, wherein at least some of said effective addresses are base real addresses not intended for translation;

means for enforcing logical partitioning of said base real addresses not intended for translation, wherein said means for enforcing logical partitioning generates partitioned real addresses from said base real addresses responsive to said state information, said partitioned real addresses lying within the portion of said real address space of said computer system of a logical partition associated with said computer processing apparatus.

16. The computer processing apparatus of claim 15, further comprising:

a plurality of sets of registers for supporting the execution of a plurality of threads, each set of registers corresponding to a respective one of said plurality of threads;

wherein said means for maintaining state information maintains state information for each of said plurality of threads independently;

wherein said means for enforcing logical partitioning of said base real addresses not intended for translation generates partitioned real addresses from said base real addresses responsive to state information for the thread associated with said base real address.