Methods and apparatuses for designing integrated circuits

• US 6,438,735 B1
• Filed: 05/17/1999
• Issued: 08/20/2002
• Est. Priority Date: 05/17/1999
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synplicity, Inc. (Synopsys Incorporated)
• Inventors: McElvain, Kenneth S., Erickson, Robert
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/310,882
• Time in Patent Office: 1,191 Days
• Field of Search: 716/5, 716/7, 716/1, 395/500.19
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTL netlist is mapped to a particular target technology (e.g. a particular IC vendor'"'"'s architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e.g. field programmable gate arrays). In an example of another method, an HDL code is compiled to produce an RTL netlist representation which specifies a plurality of ICs in which logic, designed for placement on one of the plurality of ICs, is replicated for placement on another one of the plurality of ICs. In a typical example of this method, the HDL code is written and compiled without regard to splitting the design among multiple ICs and a partition operation is performed on the RTL netlist from the results of the compiled HDL code. The partition operation produces multiple ICs and selected logic may then be replicated on the multiple ICs. In an example of another method, an HDL code is compiled to produce an RTL netlist representation which includes at least one RTL component. The one RTL component is split into multiple RTL components, each of which is designed for placement on a separate IC.

Claims

1. A method of designing a plurality of integrated circuits (ICs), said method comprising:

partitioning a technology independent RTL (register transfer level) netlist between said plurality of ICs.

2. A method as in claim 1 further comprising:

compiling a hardware description language (HDL) code, wherein said technology independent RTL netlist is produced after compiling said HDL code.

3. A method as in claim 2 wherein said ICs each comprise a programmable logic device and wherein said partitioning comprises assigning a portion of said technology independent RTL netlist to one of said plurality of ICs.

4. A method as in claim 2 further comprising:

mapping said technology independent RTL netlist to a selected technology architecture.

5. A method as in claim 4 wherein said mapping is performed after said partitioning.

6. A method as in claim 4 further comprising:

performing a place and route operation after said mapping to implement said ICs in said selected technology architecture.

7. A method as in claim 4 further comprising:

optimizing a design of each of said ICs after said partitioning.

8. A method as in claim 7 wherein said optimizing optimizes each of said ICs by removing duplicative logic or input/outputs.

9. A method as in claim 4 wherein said HDL code is created without regard to said partitioning.

10. A method as in claim 7 wherein said optimizing and said mapping are performed after said partitioning.

11. A method as in claim 4 further comprising:

mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.

12. A method as in claim 4 further comprising:

optimizing interconnects between modules of said technology independent RTL netlist before said partitioning.

13. A method as in claim 11 wherein said estimates are used to decide how to perform said partitioning.

14. A method as in claim 13 wherein a user considers said estimates and selects a command to decide how to perform said partitioning.

15. A method as in claim 4 wherein said ICs each comprise a programmable logic device and wherein said method further comprises:

testing a prototype of a system with said ICs;

performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).

16. A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising:

partitioning a technology independent RTL (register transfer level) netlist between said plurality of ICs.

17. A machine readable medium as in claim 16, wherein said method further comprises:

compiling a hardware description language (HDL) code, wherein said technology independent RTL netlist is produced after compiling said HDL code.

18. A machine readable medium as in claim 17 wherein said ICs each comprise a programmable logic device.

19. A machine readable medium as in claim 17, wherein said method further comprises:

mapping said technology independent RTL netlist to a selected technology architecture.

20. A machine readable medium as in claim 19 wherein said mapping is performed after said partitioning.

21. A machine readable medium as in claim 19, wherein said method further comprises:

performing a place and route operation after said mapping to implement said ICs in said selected technology architecture.

22. A machine readable medium as in claim 19, wherein said method further comprises:

optimizing a design of each of said ICs after said partitioning.

23. A machine readable medium as in claim 22 wherein said optimizing optimizes each of said ICs by removing duplicative logic or input/outputs.

24. A machine readable medium as in claim 19 wherein said HDL code is created without regard to said partitioning.

25. A machine readable medium as in claim 22 wherein said optimizing and said mapping are performed after said partitioning.

26. A machine readable medium as in claim 19, wherein said method further comprises:

mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.

27. A machine readable medium as in claim 19, wherein said method further comprises:

optimizing interconnects between modules of said technology independent RTL netlist before said partitioning.

28. A machine readable medium as in claim 26 wherein said estimates are used to decide how to perform said partitioning.

29. A machine readable medium as in claim 28 wherein a user considers said estimates and selects a command to decide how to perform said partitioning.

30. A machine readable medium as in claim 19 wherein said ICs each comprise a programmable logic device and wherein said method further comprises:

testing a prototype of a system with said ICs;

performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).

31. A method of designing a plurality of integrated circuits (ICs), said method comprising:

compiling a hardware description language (HDL) code to produce an RTL netlist representation which specifies said plurality of ICs;

selecting logic designed for placement on one of said plurality of ICs and replicating said logic for placement on another one of said plurality of ICs.

32. A method as in claim 31 further comprising:

partitioning said RTL netlist representation to specify said plurality of ICs.

33. A method as in claim 32 further comprising:

mapping said RTL netlist representation to a selected technology architecture,

wherein said RTL netlist representation is technology independent.

34. A method as in claim 33 wherein each of said plurality of ICs comprises a programmable logic device.

35. A method as in claim 33 wherein said mapping is performed after said partitioning.

36. A method as in claim 35 further comprising:

performing a place and route operation after said mapping to implement logic in said plurality of ICs.

37. A method as in claim 36 further comprising:

optimizing a design of each of said plurality of ICs after said partitioning.

38. A method as in claim 31 wherein said HDL code is created without specifying a plurality of ICs.

39. A method as in claim 33 further comprising:

mapping portions of said RTL netlist representation to said selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.

40. A method as in claim 39 wherein said estimates are used to decide how to perform said selecting and replicating.

41. A method as in claim 34 further comprising:

testing a prototype of a system with said plurality of ICs;

performing, after said testing, a synthesis on said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).

42. A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising:

compiling a hardware description language (HDL) code to produce an RTL netlist representation which specifies said plurality of ICs;

selecting logic designed for placement on one of said plurality of ICs and replicating said logic for placement on another one of said plurality of ICs.

43. A machine readable medium as in claim 42, said method further comprising:

partitioning said RTL netlist representation to specify said plurality of ICs.

44. A machine readable medium as in claim 43, said method further comprising:

mapping said RTL netlist representation to a selected technology architecture,

wherein said RTL netlist representation is technology independent.

45. A machine readable medium as in claim 44, wherein each of said plurality of ICs comprises a programmable logic device.

46. A machine readable medium as in claim 44, wherein said mapping is performed after said partitioning.

47. A machine readable medium as in claim 46, said method further comprising:

performing a place and route operation after said mapping to implement logic in said plurality of ICs.

48. A machine readable medium as in claim 47, said method further comprising:

optimizing a design of each of said plurality of ICs after said partitioning.

49. A machine readable medium as in claim 42 wherein said HDL code is created without specifying a plurality of ICs.

50. A machine readable medium as in claim 44, said method further comprising:

mapping portions of said RTL netlist representation to said selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.

51. A machine readable medium as in claim 50 wherein said estimates are used to decide how to perform said selecting and replicating.

52. A machine readable medium as in claim 45, said method further comprising:

testing a prototype of a system with said plurality of ICs;

performing, after said testing, a synthesis on said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).

53. A method of designing a plurality of integrated circuits (ICs), said method comprising:

compiling a hardware description language (HDL) code to produce an RTL netlist representation;

selecting one RTL component in said RTL netlist representation and splitting said one RTL component into a first RTL component designed for placement on a first IC and a second RTL component designed for placement on a second IC.

54. A method as in claim 53 further comprising:

partitioning said RTL netlist representation to specify said first IC and said second IC.

55. A method as in claim 54 further comprising:

mapping said RTL netlist representation to a selected technology architecture,

wherein said RTL netlist representation is technology independent.

56. A method as in claim 55 wherein each of said first IC and said second IC comprises a programmable logic device.

57. A method as in claim 55 wherein said mapping is performed after said partitioning.

58. A method as in claim 57 further comprising:

performing a place and route operation after said mapping to implement logic for said first RTL component for placement on said first IC and to implement logic for said second RTL component for placement on said second IC.

59. A method as in claim 55 wherein said one RTL component is created as a unitary object after said compiling.

60. A method as in claim 55 wherein said one RTL component is a large RTL component having more inputs/outputs than is available on said first IC or said second IC.

61. A method as in claim 55 further comprising:

mapping portions of said RTL netlist representation to said selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.

62. A method as in claim 61 wherein said selecting and said splitting are performed after said compiling and before said mapping.

63. A method as in claim 62 wherein said estimates are used to determine how to split said, one RTL component.

64. A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising:

compiling a hardware description language (HDL) code to produce an RTL netlist representation;

selecting one RTL component in said RTL netlist representation and splitting said one RTL component into a first RTL component designed for placement on a first IC and a second RTL component designed for placement on a second IC.

65. A machine readable medium as in claim 64, wherein said method further comprises:

partitioning said RTL netlist representation to specify said first IC and said second IC.

66. A machine readable medium as in claim 65, wherein said method further comprises:

mapping said RTL netlist representation to a selected technology architecture, wherein said RTL netlist representation is technology independent.

67. A machine readable medium as in claim 66 wherein each of said first IC and said second IC comprises a programmable logic device.

68. A machine readable medium as in claim 66 wherein said mapping is performed after said partitioning.

69. A machine readable medium as in claim 68, wherein said method further comprises:

performing a place and route operation after said mapping to implement logic for said first RTL component for placement on said first IC and to implement logic for said second RTL component for placement on said second IC.

70. A machine readable medium as in claim 66 wherein said one RTL component is created as a unitary object after said compiling.

71. A machine readable medium as in claim 66 wherein said one RTL component is a large RTL component having more inputs/outputs than is available on said first IC or said second IC.

72. A machine readable medium as in claim 66, wherein said method further comprises:

mapping portions of said RTL netlist representation to said selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.

73. A machine readable medium as in claim 72 wherein said selecting and said splitting are performed after said compiling and before said mapping.

74. A machine readable medium as in claim 73 wherein said estimates are used to determine how to split said one RTL component.

75. A method of designing a plurality of integrated circuits (ICs), said method comprising:

assigning a first portion of a technology independent RTL (register transfer level) netlist for placement on a first IC of said plurality of ICs;

assigning a second portion of said technology independent RTL netlist to a second IC of said plurality of ICs.

76. A method as in claim 75 further comprising:

compiling a hardware description language (H DL) code, wherein said technology independent RTL netlist is produced after compiling said HDL code.

77. A method as in claim 76 wherein said ICs each comprise a programmable logic device.

78. A method as in claim 76 further comprising:

mapping said technology independent RTL netlist to a selected technology architecture.

79. A method as in claim 78 wherein said mapping is performed after said assigning.

80. A method as in claim 78 further comprising:

performing a place and route operation after said mapping to implement said ICs in said selected technology architecture.

81. A method as in claim 78 further comprising:

optimizing a design of each of said ICs after said assigning.

82. A method as in claim 81 wherein said optimizing optimizes each of said ICs by removing duplicative logic or input/outputs.

83. A method as in claim 78 wherein said HDL code is created without regard to said assigning.

84. A method a s in claim 81 wherein said optimizing and said mapping are performed after said assigning.

85. A method as in claim 78 further comprising:

mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.

86. A method as in claim 78 further comprising:

optimizing interconnects between modules of said technology independent RTL netlist before said assigning.

87. A method as in claim 85 wherein said estimates are used to decide how to perform said assigning.

88. A method as in claim 87 wherein a user considers said estimates and selects a command to decide how to perform said assigning.

89. A method as in claim 78 wherein said ICs each comprise a programmable logic device and wherein said method further comprises:

testing a prototype of a system with said ICs;

performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).

90. A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising:

assigning a first portion of a technology independent RTL (register transfer level) netlist for placement on a first IC of said plurality of ICs;

assigning a second portion of said technology independent RTL netlist to a second IC of said plurality of ICs.

91. A machine readable medium as in claim 90 wherein said method further comprises:

compiling a hardware description language (HDL) code, wherein said technology independent RTL netlist is produced after compiling said HDL code.

92. A machine readable medium as in claim 91 wherein said ICs each comprise a programmable logic device.

93. A machine readable medium as in claim 91 wherein said method further comprises:

mapping said technology independent RTL netlist to a selected technology architecture.

94. A machine readable medium as in claim 93 wherein said mapping is performed after said assigning.

95. A machine readable medium as in claim 93 wherein said method further comprises:

performing a place and route operation after said mapping to implement said ICs in said selected technology architecture.

96. A machine readable medium as in claim 93 wherein said method further comprises:

optimizing a design of each of said ICs after said assigning.

97. A machine readable medium as in claim 96 wherein said optimizing optimizes each of said ICs by removing duplicative logic or input/outputs.

98. A machine readable medium as in claim 93 wherein said HDL code is created without regard to said assigning.

99. A machine readable medium as in claim 96 wherein said optimizing and said mapping are performed after said assigning.

100. A machine readable medium as in claim 93 wherein said method further comprises:

mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.

101. A machine readable medium as in claim 93 wherein said method further comprises:

optimizing interconnects between modules of said technology independent RTL netlist before said assigning.

102. A machine readable medium as in claim 100 wherein said estimates are used to decide how to perform said assigning.

103. A machine readable medium as in claim 102 wherein a user considers said estimates and selects a command to decide how to perform said assigning.

104. A machine readable medium as in claim 93 wherein said ICs each comprise a programmable logic device and wherein said method further comprises:

testing a prototype of a system with said ICs;

performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).