Reconfigurable logic for a computer
First Claim
1. A system comprising:
- a reconfigurable logic circuit including programmable logic, a first memory and a second memory, said first memory being arranged to store a number of logic designs each operable to configure said programmable logic;
a computer coupled to said reconfigurable logic circuit, said computer being operable to concurrently execute one or more application programs and an interface program, the one or more application programs generating a number of requests to utilize said reconfigurable logic circuit, the interface program being responsive to the requests to open a number of coexisting program interfaces between the one or more application programs and said reconfigurable logic circuit, the program interfaces each corresponding to one of the logic designs stored in said first memory;
wherein the reconfigurable logic circuit, in response to the interface program, provides a number of interface buffers in the second memory, each interface buffer corresponding to one of the program interfaces; and
wherein each provided interface buffer is operable to store data passing between the computer and the reconfigurable logic circuit.
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Accused Products
Abstract
A system is disclosed including a reconfigurable logic circuit having programmable logic, a first memory, and a second memory. The first memory stores a number of logic designs each operable to configure the programmable logic. Also included is a computer coupled to the reconfigurable logic circuit that concurrently executes one or more application programs and an interface program. The application programs generate a number of requests to utilize the reconfigurable logic circuit and the interface program responds to the requests by opening a number of coexisting program interfaces. These interfaces each correspond to an instance of one of the logic designs stored in the first memory. The reconfigurable logic circuit is responsive to the interface program to provide a number of interface buffers in the second memory that each belong to a corresponding one of the interfaces and are each operable to store data passing between the computer and the reconfigurable logic circuit.
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Citations
65 Claims
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1. A system comprising:
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a reconfigurable logic circuit including programmable logic, a first memory and a second memory, said first memory being arranged to store a number of logic designs each operable to configure said programmable logic;
a computer coupled to said reconfigurable logic circuit, said computer being operable to concurrently execute one or more application programs and an interface program, the one or more application programs generating a number of requests to utilize said reconfigurable logic circuit, the interface program being responsive to the requests to open a number of coexisting program interfaces between the one or more application programs and said reconfigurable logic circuit, the program interfaces each corresponding to one of the logic designs stored in said first memory;
wherein the reconfigurable logic circuit, in response to the interface program, provides a number of interface buffers in the second memory, each interface buffer corresponding to one of the program interfaces; and
wherein each provided interface buffer is operable to store data passing between the computer and the reconfigurable logic circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system, comprising:
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a digital processor bus operable to interconnect a processor cluster;
a reconfigurable logic device;
a main memory;
one or more processors coupled to said reconfigurable logic device and said main memory by said processor bus, at least one of said one or more processors being operable to access said reconfigurable logic device;
an input/output bridge coupled to said processor bus;
an input/output bus coupled to said input/output bridge to isolate said input/output bus from said processor bus;
an input/output module coupled to said input/output bus; and
wherein at least one of said one or more processors transfers data to said reconfigurable logic device with a first latency time and to said input/output module with a second latency time, said second latency time being greater than said first latency time. - View Dependent Claims (9, 10, 11, 12)
said programmable logic includes a volatile field programmable gate array;
said reconfigurable logic device includes nonvolatile loading logic coupled between said programmable logic and said first memory to load said programmable logic with a selected one the logic designs; and
said programmable logic is programmed to include a first portion with logic to interface with said computer, a second portion with logic to interface with said second memory, and a third portion to be variably configured in accordance with the selected one of the logic designs.
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11. The system of claim 8, wherein said at least one of the one or more processors is operable to access said reconfigurable logic device by mapping said reconfigurable logic device to one or more memory locations.
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12. The system of claim 8, wherein said input/output bus is of a PCI type and said processor bus operates with a first bandwidth and said input/output bus operates with a second bandwidth less than said first bandwidth.
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13. An apparatus, comprising:
- a reconfigurable logic circuit configured to communicate through a computer interface, said reconfigurable logic circuit including
programmable logic;
a first memory device operatively coupled to said programmable logic to store first interface information for a first logic design;
a second memory device operatively coupled to said programmable logic to store second interface information for a second logic design; and
memory interface logic operable to simultaneously provide local access to said first interface information in said first memory by said programmable logic and remote access to said second interface information in said second memory through said memory interface logic during configuration of said programmable logic with the first logic design, and change access modes to simultaneously provide local access to said second interface information in said second memory with said programmable logic and remote access to said first interface information in said first memory through said memory interface logic in response to configuring said programmable logic with said second logic design. - View Dependent Claims (14, 15, 16, 17, 18)
- a reconfigurable logic circuit configured to communicate through a computer interface, said reconfigurable logic circuit including
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19. An apparatus, comprising:
- a reconfigurable logic circuit configured with a computer interface, said reconfigurable logic circuit including
programmable logic;
a first memory to dynamically store a number of logic designs each selected to configure said programmable logic;
a second memory to dynamically store interface control information for each of the logic designs, the interface control information relating to one or more buffers allocated in said second memory for each of the logic designs to transmit data through said computer interface. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
- a reconfigurable logic circuit configured with a computer interface, said reconfigurable logic circuit including
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28. An apparatus, comprising:
- a reconfigurable logic circuit including programmable logic, design loading logic connected to said programmable logic, and one or more memory devices including;
a first memory space operable to store a number of logic designs for said programmable logic, said first memory space being accessible by said loading logic to selectively load one or more of said logic designs into said programmable logic; and
a second memory space operable to store a number of interface control structures each corresponding to a different instance of one of the logic designs, said second memory space being accessible by said programmable logic. - View Dependent Claims (29, 30, 31, 32, 33)
- a reconfigurable logic circuit including programmable logic, design loading logic connected to said programmable logic, and one or more memory devices including;
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34. A method, comprising:
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operating a computer coupled to a reconfigurable logic circuit, the reconfigurable logic circuit including programmable logic, a first memory device, and a second memory device;
storing first interface information in the first memory device for a first logic design and second interface information in the second memory for a second logic design;
providing simultaneous access to the first interface information by the programmable logic and the second interface information by the computer during operation of the programmable logic in accordance with the first logic design; and
providing simultaneous access to the second interface information by the programmable logic and the first interface information by the computer during operation of the programmable logic in accordance with the second logic design. - View Dependent Claims (35, 36, 37, 38, 39)
executing one or more application programs and an interface program on the computer; and
establishing two coexisting program interfaces between the computer and the reconfigurable logic circuit with the interface program, a first one of the program interfaces being for the first logic design and a second one of the program interfaces being for the second logic design.
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39. The method of claim 34, wherein the first interface information includes a control structure, a scratch space, a first interface buffer, and a second interface buffer and further comprising:
storing an identifier for the first logic design, a first pointer to the first interface buffer, a second pointer to the second interface buffer, data representing time of last use for the first logic design, and data relating to size of the first interface buffer and the second interface buffer in the control structure.
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40. A system, comprising:
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a reconfigurable logic circuit including programmable logic and a local memory, said local memory being operable to store interface information relating to a number of logic designs for said programmable logic;
a computer coupled to said reconfigurable logic circuit, said computer including one or more processors and a main memory coupled to said one or more processors, said computer being operable to execute one or more application programs and a interface program, the one or more application programs being operable to generate a number of requests to utilize said reconfigurable logic circuit, the interface program being responsive to the requests to control application of the logic designs to said programmable logic, the interface program being operable to selectively allocate a memory space in said main memory for overflow of said local memory. - View Dependent Claims (41, 42, 43, 44, 45, 46)
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47. A method, comprising:
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executing at least one application program and an interface program on a computer coupled to a reconfigurable logic circuit including programmable logic and a local memory;
storing several logic designs in the local memory with the interface program, the logic designs each being operable to configure the programmable logic;
opening two or more coexisting program interfaces between the at least one application program and the reconfigurable logic circuit with the interface program after said storing, the program interfaces each corresponding to a selected one of the logic designs;
writing input data to the reconfigurable logic circuit for a selected one of the program interfaces;
configuring the programmable logic with the selected one of the logic designs;
processing the input data with the programmable logic after said configuring;
reading output data from the reconfigurable logic circuit for the selected one of the program interfaces after said processing;
closing the selected one of the program interfaces after said reading with the interface program, other of the program interfaces remaining open; and
replacing a first one of the logic designs with a different logic design. - View Dependent Claims (48, 49, 50, 51, 52, 53)
allocating a memory space in the main memory with the interface program;
determining a least recently used one of the logic designs stored in the local memory with the interface program; and
storing the least recently used one of the logic designs in the memory space to provide space in the local memory to load another logic design.
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49. The method of claim 47, further comprising:
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providing a request to the interface program to process data with a designated one of the logic designs; and
determining status of the request with the interface program; and
performing a software routine to emulate the designated one of the logic designs in response to a first status of the request; and
configuring the programmable logic with the designated one of the logic designs in response to a second status of the request.
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50. The method of claim 47, wherein the selected one of the logic designs is the same for each of the program interfaces.
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51. The method of claim 47, wherein the selected one of the logic designs is different for each of the program interfaces.
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52. The method of claim 47, wherein the interface program includes a first routine to open a specified program interface, a second routine to write data to the reconfigurable logic circuit for the specified program interface, a third routine to read information from the reconfigurable logic circuit for the specified program interface, and a fourth routine to close the specified program interface.
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53. The method of claim 52, wherein the interface program includes a fifth routine to provide a designated logic design to the reconfigurable logic circuit and a sixth routine to remove the designated logic design.
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54. A method, comprising:
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operating a computer coupled to programmable logic;
concurrently executing two or more application programs with the computer, the application programs each generating at least one of a plurality of requests to utilize the programmable logic device during said executing;
processing the requests of each of the application programs with an interface program executed by the computer; and
controlling the programmable logic with the interface program to reconfigure the programmable logic device a number of times during said executing in accordance with the requests. - View Dependent Claims (55, 56, 57, 58, 59, 60)
storing a number of logic designs in the local memory;
allocating a memory space in the main memory with the interface program;
determining a least recently used one of the logic designs stored in the local memory with the interface program; and
storing the least recently used one of the logic designs in the memory space to provide space in the local memory to load another logic design.
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59. The method of claim 54, further comprising:
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determining status of one of the requests associated with a designated logic design; and
performing a software routine to emulate the designated logic design in response to a first status of the one of the requests; and
configuring the programmable logic with the designated logic design in response to a second status of the one of the requests.
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60. The method of claim 54, wherein the programmable logic includes a field programmable gate array, the programmable logic is included in a reconfigurable logic circuit, and the reconfigurable logic circuit further includes a first memory operable to store interface information and a second memory operable to store a number of logic designs for the programmable logic.
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61. A computer-readable device storing a number of instructions for execution by a computer coup led to a reconfigurable logic circuit, the reconfigurable logic circuit including programmable logic and a local memory to store a number of logic designs each operable to configure the programmable logic, the instructions being arranged to provide a interface program responsive to requests to utilize the reconfigurable logic circuit from a number of application programs executed by the computer, the interface program comprising:
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a first routine executable a number of times to open a corresponding number of coexisting program interfaces between the application programs and the reconfigurable logic circuit, said program interfaces each providing for configuration of the programmable logic with a corresponding one of a number of instances of one or more of several logic designs;
a second routine to provide input data to the reconfigurable logic circuit for a selected one of said program interfaces opened by said first routine for processing by the programmable logic when configured with said corresponding one of said instances;
a third routine to request output data from the reconfigurable logic circuit for said selected one of said program interfaces, said output data being generated by the programmable logic when configured by said corresponding one of said instances; and
a fourth routine to selectively close a specified one of said program interfaces established with said first routine, said fourth routine leaving other of said program interfaces open. - View Dependent Claims (62, 63, 64, 65)
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Specification