System and method for configuring a programmable logic device

• US 6,438,738 B1
• Filed: 09/19/2000
• Issued: 08/20/2002
• Est. Priority Date: 09/19/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Elayda, Bernardo
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/664,933
• Time in Patent Office: 700 Days
• Field of Search: 716/1-21, 713/1-2, 713/100, 710/8-14, 710/104, 717/114-119, 711/170-173
• US Class Current: 716/117
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

System and method for configuring a programmable logic device (PLD) using an automatically generated configuration control file. A control file contains directives for configuring a PLD with a configuration bitstream, wherein the directives are in a selected language. A configuration control file generator is programmed to automatically create the control file with the directives in the selected language. In another embodiment, the particular directives and sequence of the directives that are generated are dependent on a selected configuration mode for the PLD. In performing the directives, configuration control signals are applied to the PLD, and the configuration bitstream is provided to the PLD.

Claims

1. A method for configuring a programmable logic device with a configuration bitstream, comprising:

selecting a language from a predetermined set of languages;

automatically creating a control file having directives in the selected language for controlling configuration of the programmable logic device; and

responsive to interpretation of the directives, applying control signals to the programmable logic device and loading the configuration bitstream into the programmable logic device.

2. The method of claim 1, wherein the predetermined set of languages includes an assembly language.

3. The method of claim 1, wherein the predetermined set of languages includes a high-level programming language.

4. The method of claim 1, wherein the predetermined set of languages includes a command language.

5. The method of claim 1, further comprising selecting a configuration mode from a plurality of configuration modes, and wherein the directives in the control file conform to the selected configuration mode.

6. The method of claim 5, wherein the predetermined set of languages includes an assembly language.

7. The method of claim 5, wherein the predetermined set of languages includes a high-level programming language.

8. The method of claim 5, wherein the predetermined set of languages includes a command language.

9. The method of claim 1, further comprising:

automatically creating in the control file directives in the selected language for controlling readback of configuration data from the programmable logic device; and

reading back configuration data from the programmable logic device in response to interpretation of the directives for controlling readback in conjunction with applying the control signals.

10. The method of claim 9, wherein the predetermined set of languages includes an assembly language.

11. The method of claim 9, wherein the predetermined set of languages includes a high-level programming language.

12. The method of claim 9, wherein the predetermined set of languages includes a command language.

13. The method of claim 9, further comprising selecting a configuration mode from a plurality of configuration modes, and wherein the directives in the configuration control file conform to the selected configuration mode.

14. An apparatus for configuring a programmable logic device with a configuration bitstream, comprising:

means for selecting a language from a predetermined set of languages;

means for automatically creating a control file having directives in the selected language for controlling configuration of the programmable logic device; and

means for interpreting the directives in the control file, applying control signals to the programmable logic device responsive to the directives, and loading the configuration bitstream into the programmable logic device in response to the directives.

15. The apparatus of claim 14, further comprising means for selecting a configuration mode from a plurality of configuration modes, and wherein the directives in the configuration control file conform to the selected configuration mode.

16. A system for configuring a programmable logic device, comprising:

a host data processing system configured and arranged with a configuration control file generator and a configuration engine,

wherein the configuration control file generator is configured and arranged to select a language from a predetermined set of languages and automatically create a control file having directives in the selected language for controlling configuration of the programmable logic device, and

wherein the configuration engine is configured and arranged to interpret the directives and generate configuration control signals responsive to the directives; and

an interface device coupled to the host data processing system and having pins for connecting to the programmable logic device, wherein the interface device is arranged to apply control and configuration signals to the programmable logic device responsive to the configuration control signals from the configuration engine.

17. The system of claim 16, wherein the configuration control file generator is further configured and arranged to select a configuration mode from a plurality of configuration modes and generate directives in the configuration control file conforming to the selected configuration mode.

18. The system of claim 16,

wherein the configuration control file generator is further configured and arranged to automatically create in the control file directives in the selected language for controlling readback of configuration data from the programmable logic device; and

the configuration engine is further configured and arranged to generate readback control signals for reading back configuration data from the programmable logic device