High-level synthesis device high level synthesis method and recording medium with high level synthesis program
First Claim
1. A high-level synthesis device for synthesizing a specific circuit which exhibits behavior described in a behavioral description as data indicating behavior of a circuit aimed to be synthesized, comprising:
- a process extraction section for extracting an available process from all processes described in the behavioral description in accordance with the behavioral description including a description of synchronous communications between plural asynchronous processes, the available process being a process for performing data communications through a path having no loop;
a circuit synthesis section for producing partial circuits which realize respective available processes and for connecting the partial circuits with each other, in accordance with the inputted behavioral description, so as to synthesize the specific circuit; and
a delay insertion section for inserting a delay circuit into a path that connects partial circuits with each other so that data communications between the partial circuits through a plurality of paths are synchronized with each other, wherein the behavioral description includes, as the description of the synchronous communications, codes which indicate a process including a sending operation of a data and a process including a receiving operation of the data, respectively, said process extraction section includes a data transfer graph generation section for recognizing the codes in the inputted behavioral description, and generating a data transfer graph composed of nodes which represent respective processes and a directed edge which connects a starting node corresponding to the process including the sending operation with an end node corresponding to the process including the receiving operation, and said process extraction section further includes;
an order assignment section for assigning order to processes on a path through which data communications are performed, by a breadth first search starting with one of the nodes; and
an unavailable process search section for judging as to whether the end node is earlier in order than the starting node with regard to each directed edge described in the behavioral description, deciding that all nodes on a path passing through both of said nodes indicate unavailable processes when the end node is earlier in order than the starting node, and removing all of the nodes on said path.
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Abstract
A high-level synthesis device includes: a process extraction section for extracting an available process which performs data communications through a path having no loop from all processes described in an inputted behavioral description; a circuit synthesis section for producing partial circuits realizing the respective available processes and connecting the partial circuits in accordance with the inputted behavioral description so as to synthesize a circuit; and a delay insertion section for inserting a delay circuit in a path connecting partial circuits realizing the available processes so that data communications between the partial circuits through a plurality of paths are synchronized with each other. With the high-level synthesis device, it is possible to simulate synchronous communications between asynchronous processes in accordance with the inputted behavioral description including the description of the synchronous communications, and synthesize a circuit which has a small scale on the whole and operates at a high speed without providing control lines for handshaking.
29 Citations
3 Claims
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1. A high-level synthesis device for synthesizing a specific circuit which exhibits behavior described in a behavioral description as data indicating behavior of a circuit aimed to be synthesized, comprising:
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a process extraction section for extracting an available process from all processes described in the behavioral description in accordance with the behavioral description including a description of synchronous communications between plural asynchronous processes, the available process being a process for performing data communications through a path having no loop;
a circuit synthesis section for producing partial circuits which realize respective available processes and for connecting the partial circuits with each other, in accordance with the inputted behavioral description, so as to synthesize the specific circuit; and
a delay insertion section for inserting a delay circuit into a path that connects partial circuits with each other so that data communications between the partial circuits through a plurality of paths are synchronized with each other, wherein the behavioral description includes, as the description of the synchronous communications, codes which indicate a process including a sending operation of a data and a process including a receiving operation of the data, respectively, said process extraction section includes a data transfer graph generation section for recognizing the codes in the inputted behavioral description, and generating a data transfer graph composed of nodes which represent respective processes and a directed edge which connects a starting node corresponding to the process including the sending operation with an end node corresponding to the process including the receiving operation, and said process extraction section further includes;
an order assignment section for assigning order to processes on a path through which data communications are performed, by a breadth first search starting with one of the nodes; and
an unavailable process search section for judging as to whether the end node is earlier in order than the starting node with regard to each directed edge described in the behavioral description, deciding that all nodes on a path passing through both of said nodes indicate unavailable processes when the end node is earlier in order than the starting node, and removing all of the nodes on said path.
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2. A high-level synthesis method for synthesizing a specific circuit which exhibits behavior described in a behavioral description as data indicating behavior of a circuit aimed to be synthesized, comprising the steps of:
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extracting an available process from all processes described in the behavioral description in accordance with the behavioral description including a description of synchronous communications between plural asynchronous processes, the available process being a process for performing data communications through a path having no loop;
synthesizing the specific circuit by producing partial circuits which realize respective available processes and by connecting the partial circuits with each other, in accordance with the inputted behavioral description; and
inserting a delay circuit into a path that connects partial circuits with each other so that data communications performed between the partial circuits through a plurality of paths are synchronized with each other, wherein the behavioral description includes, as the description of the synchronous communications, codes which indicate a process including a sending operation of a data and a process including a receiving operation of the data, respectively, the step of extracting an available process includes the step of recognizing the codes in the inputted behavioral description so as to generate a data transfer graph composed of nodes which represents respective processes and a directed edge which connects a starting node corresponding to the process including the sending operation with an end node corresponding to the process including the receiving operation, and the step of extracting an available process further includes the steps of;
assigning order to processes placed on a path through which data communications are performed, by a breadth first search starting with-one of the nodes; and
judging as to whether the starting node is earlier in order than the end node with regard to each directed edge described in the behavioral description, deciding that all nodes on a path passing through both of said nodes indicate unavailable processes when the starting node is earlier in order than the end node, and removing all of the nodes on said path.
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3. A recording medium storing a high-level synthesis program for synthesizing a specific circuit which exhibits behavior described in a behavioral description as data indicating behavior of a circuit aimed to be synthesized, the high-level synthesis program comprising:
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extracting an available process from all processes described in the behavioral description in accordance with the behavioral description including a description of synchronous communications between plural asynchronous processes, the available process being a process for performing data communications through a path having no loop;
synthesizing the specific circuit by producing partial circuits which realize respective available processes and by connecting the partial circuits with each other, in accordance with the inputted behavioral description; and
inserting a delay circuit into a path that connects partial circuits with each other so that data communications performed between the partial circuits through a plurality of paths are synchronized with each other, wherein the behavioral description includes, as the description of the synchronous communications, codes which indicate a process including a sending operation of a data and a process including a receiving operation of the data, respectively, the high-level synthesis program recognizes the codes in the inputted behavioral description, and generates a data transfer graph composed of nodes which represents respective processes and a directed edge which connects a starting node corresponding to the process including the sending operation with an end node corresponding to the process including the receiving operation, and the high-level synthesis program assigns order to processes placed on a path through which data communications are performed, by a breadth first search starting with one of the nodes, after generating the data transfer graph; and
judging as to whether the end node is earlier in order than the starting node with regard to each directed edge described in the behavioral description, deciding that all nodes on a path passing through both of said nodes indicate unavailable processes when the end node is earlier in order than the starting node, and removing all of the nodes on said path.
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Specification