Method for improving seed layer electroplating for semiconductor

• US 6,440,289 B1
• Filed: 04/02/1999
• Issued: 08/27/2002
• Est. Priority Date: 04/02/1999
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Woo, Christy Mei-Chu, Singh, Bhanwar, Rangarajan, Bharath
• Primary Examiner(s): Nguyen, Nam
• Assistant Examiner(s): Leader, William T.
• Application Number:
  US09/285,334
• Time in Patent Office: 1,243 Days
• Field of Search: 205/102, 205/103, 205/104, 205/123, 205/125, 205/184, 205/186, 205/187, 205/157
• US Class Current: 205/103
• CPC Class Codes: C25D 5/18 Electroplating using modulated, pulsed or reversing current
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers

Abstract

A method is provided of forming a semiconductor seed layer starting with a non-electrochemical deposition of an initial deposition of the seed layer. This is followed by a very slow deposition rate electrochemical deposition with an organic additive at the beginning of the plating process to overcome the initial thin seed coverage at the bottom and bottom sidewall of a feature. The electrochemical deposition plates at a very low rate initially followed by a low rate deposition to build up a thicker and more uniform seed layer at the bottom and bottom sidewall. In the meantime, this slow plating rate step only adds a small thickness to the top portion of the feature where non-electrochemical deposition seed coverage was initially thicker.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor with a dielectric layer formed thereon, wherein said dielectric layer overlays a region on said semiconductor;

forming an opening in said dielectric layer, said opening defined by sidewalls of said dielectric layer and a bottom exposing a portion of said region on said semiconductor;

depositing an initially deposited copper seed layer by a non-electrochemical deposition process over said dielectric layer and in said opening, including along said walls, said initially deposited copper seed layer formed to a thickness insufficient to fill said opening;

depositing a secondarily deposited copper seed layer by an electrochemical deposition process over said initially deposited copper seed layer, said depositing performed initially at a very low rate and increased to a low rate, wherein plating at the very low deposition rate is continued until under a few hundred angstroms of said copper seed layer have been deposited and plating at the low rate is continued until the copper deposited on the sidewalls of said opening meets copper deposited on the bottom; and

depositing copper material in contact with said secondarily deposited seed layer by a third process to substantially fill said opening.

2. The method as claimed in claim 1 wherein depositing said secondarily deposited seed layer is performed in an electrochemical deposition process using an organic additive and very low and low depositions to control deposition in selected regions of said opening.

3. The method as claimed in claim 1 wherein depositing said secondarily deposited copper seed layer is performed using a very low deposition rate of about two to fifteen angstroms per second followed by a low deposition rate of about thirty to forty angstroms per second.

4. The method as claimed in claim 1 wherein depositing said secondarily deposited copper seed layer is performed using a very low deposition rate of about two to fifteen angstroms per second followed by a low deposition rate of about thirty to forty angstroms per second and wherein the very low deposition rate deposits about two to three hundred angstroms of said copper seed layer.

5. The method as claimed in claim 1 wherein depositing said secondarily deposited copper seed layer is performed using a very low direct current to deposit at two to fifteen angstroms per second followed by a low direct current to deposit at thirty to forty angstroms per second.

6. The method as claimed in claim 1 wherein depositing said secondarily deposited copper seed layer is performed using a very low forward pulse current to deposit at two to fifteen angstroms per second followed by a low forward pulse current to deposit at thirty to forty angstroms per second.

7. The method as claimed in claim 1 wherein depositing said secondarily deposited seed layer is performed using a very low bi-directional pulse current of forward and reverse pulses to deposit at two to fifteen angstroms per second followed by a low bi-directional current of forward and reverse pulses to deposit at thirty to forty angstroms per second.

8. The method as claimed in claim 1 wherein depositing said secondarily deposited seed layer and said coppen material are performed at a very low deposition rate of about two to fifteen angstroms per second, a low deposition rate of about thirty to forty angstroms per second, and a high deposition rate of sixty to one hundred angstroms per second.

9. The method as claimed in claim 1 including depositing an adhesive/barrier layer over said dielectric layer and in said opening, including along said walls, said adhesive/barrier layer formed to a thickness insufficient to fill said opening;

said adhesive/barrier layer deposited before depositing said initially deposited seed layer.