N-profile engineering at the poly/gate oxide and gate oxide/SI interfaces through NH3 annealing of a layered poly/amorphous-silicon structure

• US 6,440,829 B1
• Filed: 12/30/1998
• Issued: 08/27/2002
• Est. Priority Date: 12/30/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Laughery, Michael A., Ma, Yi, Roy, Pradip K.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): EATON, KURT M
• Application Number:
  US09/223,354
• Time in Patent Office: 1,336 Days
• Field of Search: 438/652, 438/565, 438/542, 438/921, 438/922, 438/923, 438/585, 438/775, 438/660, 438/592, 438/657, 438/653, 438/588
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916

Abstract

A method and structure providing N-profile engineering at the poly/gate oxide and gate oxide/Si interfaces of a layered polysilicon/amorphous silicon structure of a semiconductor device. NH₃ annealing provides for the introduction of nitrogen to the interface, where the nitrogen suppresses Boron diffusion, improves gate oxide integrity, and reduces the sites available for trapping hot carriers which degrade device performance.

Claims

1. A method for forming a semiconductor structure within a semiconductor device, comprising the steps of:

a. providing a semiconductor substrate;

b. forming a dielectric film on said substrate, said dielectric film having an upper surface;

c. sequentially forming a plurality of semiconductor sublayers including a bottom semiconductor sublayers on said upper surface of said dielectric film, said plurality of semiconductor sublayers including a bottom semiconductor sublayer having a lower surface forming an interface region with said upper surface of said dielectric film and thereby forming a layered structure; and

d. adding nitrogen to said interface region by annealing said layered structure in NH₃ not prior to the completion of said step of sequentially forming said plurality of semiconductor sublayers.

2. The method as in claim 1, wherein said forming a dielectric film comprises thermally oxidizing said substrate.

3. The method as in claim 2, wherein said step of forming a doped semiconductor layer comprises forming a gate electrode of a transistor, and said step of thermally oxidizing said substrate comprises forming a gate oxide of said transistor.

4. The method as in claim 1, in which step c) further includes introducing a dopant impurity other than nitrogen into said layered structure.

5. The method as in claim 4, wherein said dopant impurity comprises boron.

6. The method as in claim 1, wherein said sequentially forming a plurality of semiconductor sublayers includes forming at least one polycrystalline sublayer, and forming at least one amorphous silicon sublayer.

7. The method as in claim 6, wherein said bottom semiconductor sublayer comprises amorphous silicon.

8. The method as in claim 6, wherein said bottom semiconductor sublayer comprises polycrystalline silicon.

9. The method as in claim 6, in which step d) includes simultaneously converting at least part of each of said at least one amorphous silicon sub layer to a converted polycrystalline silicon sublayer.

10. The method as in claim 1, in which step c) further includes doping at least one of said plurality of semiconductor sublayers with a dopant impurity species being other than nitrogen.

11. The method as in claim 10, wherein said doping comprises doping with boron.

12. The method as in claim 1, further comprising the step e) of forming a silicide film on said doped semiconductor layer.

13. The method as in claim 12, wherein said silicide film comprises a metal silicide including a metal selected from the group of cobalt, tungsten, titanium, molybdenum, and tantalum.

14. The method as in claim 12, in which step d) includes creating a pattern of said doped semiconductor layer to form a transistor gate and to expose a surface of said substrate, and forming source and drain regions within said surface, and step e) includes simultaneously forming a silicide film on said source and drain regions.

15. The method as in claim 1, wherein said annealing comprises annealing at a temperature within a range of 700°

C. to 900°

C.

16. The method as in claim 1, wherein said annealing comprises annealing at a pressure less than one Torr.

17. The method as in claim 1, wherein said annealing comprises annealing for a time within the range of 15 minutes to 60 minutes.

18. The method as in claim 1, in which step d) includes providing a source gas including NH₃ and a carrier gas.

19. The method as in claim 18, wherein said carrier gas comprises one of argon, helium, and nitrogen.

20. The method as in claim 1, wherein said semiconductor device comprises a charge coupled device (CCD).

21. The method as in claim 1, wherein said semiconductor device comprises an electrically erasable programmable read only memory (E² PROM) device.

22. The method as in claim 1, wherein said semiconductor device comprises a CMOS device.

23. The method as in claim 1, wherein a nitrogen concentration at said interface region is within a range of 10E20-10E21 atoms/cm³.

24. A semiconductor structure formed according to the method as in claim 1.