Semiconductor integrated system

• US 6,441,399 B1
• Filed: 01/13/1999
• Issued: 08/27/2002
• Est. Priority Date: 04/22/1994
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Kawasaki, Yuji
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US09/229,677
• Time in Patent Office: 1,322 Days
• Field of Search: 257/351, 257/59, 257/72, 257/392, 257/403
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

In a monolithic active matrix circuit that uses offset-gate TFTs in which the gate electrode is offset from the source and drain regions or TFTs whose gate insulating film is formed by vapor deposition, not only an active matrix circuit but also a drive circuit therefor is formed by using P-channel TFTs.

Claims

1. A semiconductor device comprising:

a plurality of first thin film transistors for switching pixels formed over a substrate having an insulating surface;

a driver circuit comprising a plurality of second thin film transistors formed over said substrate for driving said first thin film transistors, each of said first and second thin film transistors having a channel forming region comprising crystalline silicon;

an interlayer insulating film formed over said first thin film transistors and said second thin film transistors;

a plurality of pixel electrodes formed on said interlayer insulating film and electrically connected to said first thin film transistors at one of source or drain thereof;

a plurality of wirings formed on said interlayer insulating film and electrically connected to said first thin film transistors at the other one of the source or drain thereof,

wherein all of said first and second thin film transistors are p-channel type thin film transistors.

2. The semiconductor device according to claim 1 wherein said driver circuit comprises a shift register.

3. The semiconductor device according to claim 1 wherein at least one of said second thin film transistors has its channel region doped with boron and at least another one of said second thin film transistors has its channel region not doped with boron.

4. The semiconductor device according to claim 1 wherein said pixel electrodes are transparent.

5. The semiconductor device according to claim 1 wherein said interlayer insulating film comprises silicon oxide.

6. The semiconductor device according to claim 1 wherein said interlayer insulating film comprises silicon nitride.

7. A semiconductor device comprising:

a plurality of first thin film transistors for switching pixels, formed over a substrate having an insulating surface;

a driver circuit comprising a plurality of second thin film transistors formed over said substrate for driving said first thin film transistors, each of said first and second thin film transistors comprising a crystalline semiconductor layer having source and drain regions and a channel forming region extending therebetween, a gate insulating film formed on said channel forming region and a gate electrode formed on said gate insulating film;

an interlayer insulating film formed over said first thin film transistors and said second thin film transistors;

a plurality of pixel electrodes formed on said interlayer insulating film and electrically connected to said first thin film transistors at one of source or drain thereof;

a plurality of wirings formed on said interlayer insulating film and electrically connected to said first thin film transistors at the other one of the source or drain thereof,

wherein all of said first and second thin film transistors are p-channel type film transistors.

8. The semiconductor device according to claim 7 wherein said driver circuit comprises a shift register.

9. The semiconductor device according to claim 7 wherein at least one of said second thin film transistors has its channel region doped with boron and at least another one of said second thin film transistors has its channel region not doped with boron.

10. The semiconductor device according to claim 7 wherein said pixel electrodes are transparent.

11. The semiconductor device according to claim 7 wherein said interlayer insulating film comprises silicon oxide.

12. The semiconductor device according to claim 7 wherein said interlayer insulating film comprises silicon nitride.

13. A semiconductor device comprising:

a plurality of first thin film transistors for switching pixels formed over a substrate having an insulating surface;

a driver circuit comprising a plurality of second thin film transistors formed over said substrate for driving said first thin film transistors, each of said first and second thin film transistors having a channel forming region comprising crystalline silicon;

an interlayer insulating film formed over said first thin film transistors and said second thin film transistors;

a plurality of pixel electrodes formed on said interlayer insulating film and electrically connected to said first thin film transistors at one of source or drain thereof;

a plurality of wirings formed on said interlayer insulating film and electrically connected to said first thin film transistors at the other one of the source or drain thereof; and

a semiconductor chip formed over the substrate,

wherein all of said first and second thin film transistors are p-channel type thin film transistors.

14. The semiconductor device according to claim 13 wherein said driver circuit comprises a shift register.

15. The semiconductor device according to claim 13 wherein at least one of said second thin film transistors has its channel region doped with boron and at least another one of said second thin film transistors has its channel region not doped with boron.

16. The semiconductor device according to claim 13 wherein said pixel electrodes are transparent.

17. The semiconductor device according to claim 13 wherein said interlayer insulating film comprises silicon oxide.

18. The semiconductor device according to claim 13 wherein said interlayer insulating film comprises silicon nitride.

19. The semiconductor device according to claim 13 wherein each of said first and second thin film transistors has an offset structure.

20. The semiconductor device according to claim 13 wherein said semiconductor chip is at least one of a correction memory, a memory, a CPU and an input port.

21. The semiconductor device according to claim 13 wherein each of said first and second thin film transistor has a gate electrode over the channel forming region.

22. A semiconductor device comprising:

a plurality of first thin film transistors for switching pixels formed over a substrate having an insulating surface;

a driver circuit comprising a plurality of second thin film transistors formed over said substrate for driving said first thin film transistors, each of said first and second thin film transistors having a channel forming region comprising crystalline silicon;

an interlayer insulating film formed over said first thin film transistors and said second thin film transistors;

a plurality of pixel electrodes formed on said interlayer insulating film and electrically connected to said first thin film transistors at one of source or drain thereof;

a plurality of conductors formed on said interlayer insulating film and electrically connected to said first thin film transistors at the other one of the source or drain thereof,

wherein all of said first and second thin film transistors are p-channel type thin film transistors.

23. The semiconductor device according to claim 22 wherein said pixel electrodes are transparent.

24. The semiconductor device according to claim 22 wherein said interlayer insulating film comprises silicon oxide.

25. The semiconductor device according to claim 22 wherein said interlayer insulating film comprises silicon nitride.

26. The semiconductor device according to claim 22 wherein each of said first and second thin film transistors has an offset structure.

27. The semiconductor device according to claim 22 further comprising a semiconductor chip formed over the substrate.

28. The semiconductor device according to claim 22 wherein each of said first and second thin film transistor has a gate electrode over the channel forming region.

29. A semiconductor device comprising:

a plurality of first thin film transistors for switching pixels formed over a substrate having an insulating surface;

a source driver circuit comprising a plurality of second thin film transistors formed over said substrate, each of said first and second thin film transistors having a channel forming region comprising crystalline silicon;

an interlayer insulating film formed over said first thin film transistors and said second thin film transistors;

a plurality of pixel electrodes formed on said interlayer insulating film and electrically connected to said first thin film transistors at one of source or drain thereof;

a plurality of conductors formed on said interlayer insulating film and electrically connected to said first thin film transistors at the other one of the source or drain thereof,

wherein all of said first and second thin film transistors are p-channel type thin film transistors.

30. The semiconductor device according to claim 29 wherein said pixel electrodes are transparent.

31. The semiconductor device according to claim 29 wherein said interlayer insulating film comprises silicon oxide.

32. The semiconductor device according to claim 29 wherein said interlayer insulating film comprises silicon nitride.

33. The semiconductor device according to claim 29 wherein each of said first and second thin film transistors has an offset structure.

34. The semiconductor device according to claim 29 further comprising a semiconductor chip formed over the substrate.

35. The semiconductor device according to claim 29 wherein each of said first and second thin film transistor has a gate electrode over the channel forming region.

36. A semiconductor device comprising:

a plurality of first thin film transistors for switching pixels formed over a substrate having an insulating surface;

a gate driver circuit comprising a plurality of second thin film transistors formed over said substrate, each of said first and second thin film transistors having a channel forming region comprising crystalline silicon;

an interlayer insulating film formed over said first thin film transistors and said second thin film transistors;

a plurality of pixel electrodes formed on said interlayer insulating film and electrically connected to said first thin film transistors at one of source or drain thereof;

a plurality of conductors formed on said interlayer insulating film and electrically connected to said first thin film transistors at the other one of the source or drain thereof,

wherein all of said first and second thin film transistors are p-channel type thin film transistors.

37. The semiconductor device according to claim 36 wherein said pixel electrodes are transparent.

38. The semiconductor device according to claim 36 wherein said interlayer insulating film comprises silicon oxide.

39. The semiconductor device according to claim 36 wherein said interlayer insulating film comprises silicon nitride.

40. The semiconductor device according to claim 36 wherein each of said first and second thin film transistors has an offset structure.

41. The semiconductor device according to claim 36 further comprising a semiconductor chip formed over the substrate.

42. The semiconductor device according to claim 36 wherein each of said first and second thin film transistor has a gate electrode over the channel forming region.

43. A semiconductor device comprising:

a plurality of first thin film transistors for switching pixels formed over a substrate having an insulating surface;

a source driver circuit comprising a plurality of second thin film transistors formed over said substrate, each of said first and second thin film transistors having a channel forming region comprising crystalline silicon;

an interlayer insulating film formed over said first thin film transistors and said second thin film transistors;

a plurality of pixel electrodes formed on said interlayer insulating film and electrically connected to said first thin film transistors at one of source or drain thereof;

a plurality of wirings formed on said interlayer insulating film and electrically connected to said first thin film transistors at the other one of the source or drain thereof,

wherein all of said first and second thin film transistors are p-channel type thin film transistors.

44. The semiconductor device according to claim 43 wherein said pixel electrodes are transparent.

45. The semiconductor device according to claim 43 wherein said interlayer insulating film comprises silicon oxide.

46. The semiconductor device according to claim 43 wherein said interlayer insulating film comprises silicon nitride.

47. The semiconductor device according to claim 43 wherein each of said first and second thin film transistors has an offset structure.

48. The semiconductor device according to claim 43 further comprising a semiconductor chip formed over the substrate.

49. The semiconductor device according to claim 43 wherein each of said first and second thin film transistor has a gate electrode over the channel forming region.

50. A semiconductor device comprising:

a plurality of first thin film transistors for switching pixels formed over a substrate having an insulating surface;

a gate driver circuit comprising a plurality of second thin film transistors formed over said substrate, each of said first and second thin film transistors having a channel forming region comprising crystalline silicon;

an interlayer insulating film formed over said first thin film transistors and said second thin film transistors;

a plurality of pixel electrodes formed on said interlayer insulating film and electrically connected to said first thin film transistors at one of source or drain thereof;

a plurality of wirings formed on said interlayer insulating film and electrically connected to said first thin film transistors at the other one of the source or drain thereof,

wherein all of said first and second thin film transistors are p-channel type thin film transistors.

51. The semiconductor device according to claim 50 wherein said pixel electrodes are transparent.

52. semiconductor device according to claim 50 wherein said interlayer insulating film comprises silicon oxide.

53. The semiconductor device according to claim 50 wherein said interlayer insulating film comprises silicon nitride.

54. The semiconductor device according to claim 50 wherein each of said first and second thin film transistors has an offset structure.

55. The semiconductor device according to claim 50 further comprising a semiconductor chip formed over the substrate.

56. The semiconductor device according to claim 50 wherein each of said first and second thin film transistor has a gate electrode over the channel forming region.