Ferroelectric and paraelectric thin film devices using dopants which eliminate ferroelectricity

• US 6,441,415 B1
• Filed: 06/25/1999
• Issued: 08/27/2002
• Est. Priority Date: 06/25/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Yamanaka, Stacey A., Lakeman, Charles D. E., Summerfelt, Scott R., Moise, Theodore S., Gilbert, Stephen R.
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US09/344,580
• Time in Patent Office: 1,159 Days
• Field of Search: 257/295, 257/310, 365/145, 438/3, 438/240
• US Class Current: 257/295
• CPC Class Codes: H01L 28/55 with a dielectric comprising a perovskite structure material
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A method for simultaneously producing areas of paraelectric states and areas of ferroelectric states on a single thin film layer, thereby reducing the number of processing steps required to produce integrated chips containing both standard capacitors and non-volatile memory devices from the number of steps needed using the conventional approach. A device containing both ferroelectric capacitors and non-ferroelectric capacitors using a single thin film as the dielectric.

Claims

1. An integrated chip comprising a dielectric layer formed from a single thin film dielectric layer containing both ferroelectric areas and paraelectric areas, wherein said dielectric layer in said paraelectric areas also contains dopants which eliminate ferroelectricity.

2. The integrated chip of claim 1, wherein said thin-film dielectric layer is a perovskite compound.

3. The integrated chip of claim 1, wherein said thin-film dielectric layer is discontinuous.

4. An integrated chip containing both non-ferroelectric capacitor devices and ferroelectric memory devices, wherein the dielectric for both said non-ferroelectric capacitor devices and said ferroelectric memory devices is formed from a single thin-film dielectric layer, and wherein said dielectric layer in said non-ferroelectric capacitor devices also contains dopants which eliminate ferroelectricity .

5. The integrated chip of claim 4, wherein said thin-film dielectric layer is a perovskite compound.