Fan-out translator for a semiconductor package

• US 6,441,488 B1
• Filed: 07/27/2000
• Issued: 08/27/2002
• Est. Priority Date: 05/30/1997
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Smith, John W.
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/627,111
• Time in Patent Office: 761 Days
• Field of Search: 257/738, 257/737, 257/734, 257/777-780, 257/787, 257/786, 257/784, 257/692, 257/693, 257/686, 257/685, 324/754, 324/755, 324/761, 324/762, 324/765
• US Class Current: 257/738
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/0394 Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• CPC Class Codes: H05K 2201/049 PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/09472 Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2203/041 Solder preforms in the shape of solder balls soldering leadless components having an array of bottom contacts H05K3/3436
• CPC Class Codes: H05K 3/0058 Laminating printed circuit boards onto other substrates, e.g. metallic substrates H05K1/0281 takes precedence

Abstract

A translator for connecting package terminals of a semiconductor chip package to connection pads on a substrate is disclosed. The package terminals are arranged in an array on the semiconductor chip package and the connection pads are arranged in an array on the substrate. The package terminals have a first pitch and the connection pads have a second pitch. The translator has a sheet-like support element with central region and a peripheral region which is more rigid than the central region. First translator terminals are exposed at a first surface of the support element, in the central region. Second translator terminals are exposed at a second surface of the support element, in the peripheral region. The first translator terminals have the first pitch so as to correspond to the package terminals and the second translator terminals have the second pitch so as to correspond to the connection pads. The first and second pitch are different. Traces are provided on the support element and are adapted to connect the package terminals to the first translator terminals.

Claims

1. A translator for connecting a plurality of package terminals arranged in an array on a semiconductor chip package and a plurality of connection pads arranged in an array on a substrate, the package terminals having a first pitch and the connection pads having a second pitch, comprising:

a. a flexible, sheet-like support element having a first surface, a second surface opposite the first surface, a peripheral region, and a central region defined by the peripheral region, said peripheral region being more rigid than the central region,

b. a plurality of first translator terminals arranged in an array having the first pitch so as to correspond to the package terminals, disposed on the central region, and exposed at the first surface of the support element;

c. a plurality of second translator terminals arranged in an array having the second pitch so as to correspond to the connection pads, disposed on at least the peripheral region of the support element, and exposed at the second surface; and

d. a plurality of traces disposed on the support element, said traces being adapted to electrically interconnect the package terminals to the first translator terminals;

wherein the first pitch and the second pitch are different.

2. The translator of claim 1, wherein the peripheral region of the support element is comprised of a flexible, sheet-like layer and a stiffener disposed over the sheet-like layer.

3. The translator of claim 2, wherein the stiffener has a central hole disposed over the central region of the support element.

4. The translator of claim 3, further comprising a compliant ring disposed between the stiffener and the flexible, sheet-like layer,

5. The electronic assembly of claim 4, wherein the compliant ring is comprised of a material selected from the group consisting of silicone gels, silicone elastomers and flexiblized epoxies.

6. The electronic assembly of claim 1, wherein the array of first translator terminals are disposed on the first surface of the support element.

7. The translator of claim 1, further comprising a heat spreader disposed over the support element.

8. The translator of claim 1, wherein the support element further comprises at least one feature selected from the group consisting of ground planes and potential power planes.

9. The translator of claim 1, wherein the support element further comprises a plurality of holes arranged in an array corresponding to the first pitch;

and each of the first translator terminals is disposed over one of the holes, extends inwardly over the hole and is adapted to resiliently engage one of the package terminals.

10. The translator of claim 9, wherein the peripheral region of the support element is comprised of a flexible, sheet-like layer and a stiffener disposed over the sheet-like layer.

11. The socket of claim 9, wherein the stiffener has a central hole disposed over the central region of the support element.

12. The translator of claim 11, further comprising a compliant ring disposed between the stiffener and the flexible, sheet-like layer.

13. The translator of claim 12, wherein the compliant ring is comprised of a material selected from the group consisting of silicone gels, silicone elastomers and flexiblized epoxies.

14. The translator of claim 9, wherein the array of first translator terminals are disposed on the first surface of the support element.

15. The translator of claim 9, further comprising a heat spreader disposed over the support element.

16. The translator of claim 9, wherein the support element further comprises a least one feature selected from the group consisting of ground planes and potential power planes.