Programmable logic device with partial battery backup

• US 6,441,641 B1
• Filed: 11/28/2000
• Issued: 08/27/2002
• Est. Priority Date: 11/28/2000
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wong, Jennifer, Goetting, F. Erich, Shimanek, Schuyler E., Sowards, Jane W., Pang, Raymond C., Alfke, Peter H., Kondapalli, Venu M., Frake, Scott O.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TRAN, ANH Q
• Application Number:
  US09/724,735
• Time in Patent Office: 637 Days
• Field of Search: 326/37-41, 326/46
• US Class Current: 326/41
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.

Claims

1. A PLD comprising:

a logic portion powered by an external power supply;

a plurality of memory registers; and

a switching structure comprising a voltage level shift circuit for switching between connecting a battery pad to the plurality of memory registers and connecting the external power supply to the plurality of memory registers.

2. The PLD of claim 1 wherein the plurality of memory registers comprise registers for storing at least one encryption key.

3. The PLD of claim 1 wherein the plurality of memory registers comprise flip flops for storing data generated while operating the PLD.

4. The PLD of claim 3 wherein the plurality of memory registers further comprise latches for storing lookup tables in the PLD.

5. The PLD of claim 1 wherein the plurality of memory registers comprise registers for storing configuration data for configuring the PLD.

6. The PLD of claim 1 wherein the switching structure comprises:

a detection circuit for detecting when the external power supply is providing a sufficient voltage; and

a pull-down device controlled from the battery pad to allow only the battery pad to be connected to an output terminal when the external power supply is not providing a sufficient voltage.