Frequency-doubling delay locked loop

• US 6,441,659 B1
• Filed: 05/01/2000
• Issued: 08/27/2002
• Est. Priority Date: 04/30/1999
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Demone, Paul W.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): NGUYEN, LINH M
• Application Number:
  US09/562,024
• Time in Patent Office: 848 Days
• Field of Search: 327/149, 327/153, 327/158, 327/161, 327/162, 327/156, 327/147, 327/271, 327/272, 327/276, 327/277, 327/261, 327/113, 327/116, 327/119, 331/1.A, 331/17, 375/375, 375/376, 375/269, 375/270
• US Class Current: 327/156
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: H03K 5/15046 using a tapped delay line
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Abstract

A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Claims

1. A delay locked loop for generating an output clock signal in response to a reference input clock signal comprising:

a) a delay line having a predetermined number of serially coupled delay stages, each of said delay stages providing a delay stage tap output;

b) a plurality of combining circuit cells, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each of said combining cells providing first and second complementary outputs, said outputs of each cell being separated in time by said predetermined number of delay stages and having a multiplied frequency of said reference input clock signal;

c) a selector responsive to a selection control signal for selecting an output from one of a pair of complementary outputs of one of said combining cells, to produce said output clock signal;

d) a phase detector responsive to said output clock signal and said reference input clock signal to control said selector for selecting an optimum complimentary output for synchronizing said reference input clock signal and said output clock signal.

2. A delay locked loop as described in claim 1, including N serially coupled delay stages providing N tap outputs to N/4 combining circuit cells and said N/4 combining cells provide N/2 evenly spaced phases of the output clock signal whose frequency is twice that of the reference input clock.

3. A delay locked loop as described in claim 1, wherein each of said combining circuit cells are responsive to a rising edge of a pulse of said input clock for initiating a rising pulse of said output clock and responsive to a delayed version of said input pulse for clearing said pulse and responsive to a falling edge of said input clock pulse to initiate a rising edge of a second output pulse and responsive to a delayed version of said input falling edge for clearing said second output pulse.

4. A delay locked loop as described in claim 1, wherein said optimum complementary output is an output whose phase is a closest match to said input reference clock signal'"'"'s phase.

5. A frequency multiplier circuit for generating an output clock signal in response to a rising edge of a reference input clock signal, said multiplier comprising:

a delay line for receiving and delaying said reference input clock signal, said delay line having a plurality of serially coupled delay stages each having a delay stage tap output;

a plurality of combining circuit cells, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each of the combining cells providing first and second complementary outputs, the outputs of each cell being separated in time by said predetermined number of delay stages and having a multiplied frequency of said reference input clock signal;

a selector coupled to said combining cell outputs for selecting an output from said combining cells outputs for producing said output clock signal;

wherein said frequency multiplier circuit is a delay locked loop;

wherein the number of said plurality of combining cells is divisible by 4;

wherein each of said delay stage outputs coupled to said combining cell inputs is

separated by at least 90 degrees; and

,

wherein said combining cells comprising a flip-flop circuit for producing said combining cell output.

6. A frequency multiplier circuit as described in claim 5, wherein said plurality of combining cells further comprise:

a) a first pair of edge detectors comprising a rising edge detector and a falling edge detector coupled to selective ones of said delay stage outputs for providing a first and second set signals;

b) a second pair of said rising and falling edge detectors coupled to selective ones of said delay stage outputs for providing a first and second reset signals;

c) a first OR gate for combining said first and second set signals, producing a common set signal;

d) a second OR gate for combining said first and second reset signals, producing a common reset signal; and

e) a flip-flop circuit for receiving said common set and reset signals and for providing a signal having a multiplied frequency of said input clock signal.

7. A frequency multiplier circuit as described in claim 5, further comprising a phase detector for receiving said output clock signal and said reference input clock signal for controlling said selector for synchronizing said reference input clock signal and said output clock signal.

8. A method for generating an output clock signal in response to a rising edge of a reference input clock signal, said method comprising the steps of:

a) receiving and delaying said reference input clock signal using a plurality of serially coupled delay stages each having a delay stage tap output;

b) providing a plurality of output signals, each having a multiplied frequency of said reference input clock signal using a plurality of combining circuit cells, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs; and

c) selecting an output from said combining cell outputs for producing said output clock signal, wherein said selected combining cell output has a phase closest to said input reference signal'"'"'s phase.