SOI CMOS Schmitt trigger circuits with controllable hysteresis
First Claim
1. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis comprising:
- a stack of a plurality of field effect transistors (FETs) connected in series between a voltage supply and ground;
an input applied to a gate of each of said stack of said plurality of field effect transistors (FETs);
said stack of a plurality of field effect transistors (FETs) providing an output at a junction of a predetermined pair of said plurality of field effect transistors (FETs);
at least one feedback field effect transistor (FET), each feedback FET having a source coupled a junction of a predefined pair of said plurality of field effect transistors (FETs) and having a gate coupled to said output; and
a FET floating body of each of said stack of said plurality of field effect transistors (FETs) being connected to a voltage supply rail.
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Accused Products
Abstract
A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis and a method are provided for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications. A SOI CMOS Schmitt trigger circuit with controllable hysteresis includes a stack of a plurality of field effect transistors (FETs) connected in series between a voltage supply and ground. An input is applied to a gate of each of the stack of the plurality of field effect transistors (FETs). The stack of the plurality of field effect transistors (FETs) provides an output at a junction of a predetermined pair of the plurality of field effect transistors (FETs). At least one feedback field effect transistor (FET) has a source coupled a junction of a predefined pair of the stack of field effect transistors (FETs) and has a gate coupled to the output. A FET body of each of the stack of the plurality of field effect transistors (FETs) is connected to a voltage supply rail. The stack of the plurality of field effect transistors (FETs) includes a plurality of P-channel field effect transistors (PFETs) and a plurality of N-channel field effect transistors (NFETs). The FET body of each of the plurality of P-channel field effect transistors (PFETs) is connected to a positive voltage supply rail and the FET body of each of the plurality of N-channel field effect transistors (NFETs) is connected to a voltage supply ground rail. The FET body of a P-channel feedback field effect transistor (PFET) is connected to one of a positive voltage supply rail, the gate or the source of the feedback PFET. The FET body of a N-channel feedback field effect transistor (NFET) is connected to one of a voltage supply ground rail, the gate or the source of the feedback NFET. A successive switching threshold adjustment technique is provided. Additional successive switching threshold adjustment is achieved by successive tapping of NFET or PFET feedback devices for the V+ or the V− trigger edges, respectively. With this arrangement, higher V+ and lower V− are realized without using excessively wide NFET or PFET feedback devices.
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Citations
20 Claims
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1. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis comprising:
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a stack of a plurality of field effect transistors (FETs) connected in series between a voltage supply and ground;
an input applied to a gate of each of said stack of said plurality of field effect transistors (FETs);
said stack of a plurality of field effect transistors (FETs) providing an output at a junction of a predetermined pair of said plurality of field effect transistors (FETs);
at least one feedback field effect transistor (FET), each feedback FET having a source coupled a junction of a predefined pair of said plurality of field effect transistors (FETs) and having a gate coupled to said output; and
a FET floating body of each of said stack of said plurality of field effect transistors (FETs) being connected to a voltage supply rail. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis comprising:
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a stack of a plurality of field effect transistors (FETs) connected in series between a voltage supply and ground;
an input applied to a gate of each of said stack of said plurality of field effect transistors (FETs);
said stack of a plurality of field effect transistors (FETs) providing an output at a junction of a predetermined pair of said plurality of field effect transistors (FETs);
a FET floating body of each of said stack of said plurality of field effect transistors (FETs) being connected to a voltage supply rail; and
at least one feedback field effect transistor (FET), said at least one feedback field effect transistor (FET) including a plurality of P-channel field effect transistors (PFETs), said plurality of feedback PFETs connected between a predefined pair of said plurality of field effect transistors (FETs) and said output; and
each of said plurality of feedback PFETs having a source coupled to a respective junction of a respective pair of said plurality of field effect transistors (FETs) and having a gate coupled to a respective next junction of a next successive pair of said plurality of field effect transistors (FETs);
said plurality of feedback PFETs for threshold adjustment of a V−
switching trip point of the SOI CMOS Schmitt trigger circuit.
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13. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) Schmitt trigger circuit with controllable hysteresis comprising:
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a stack of a plurality of field effect transistors (FETs) connected in series between a voltage supply and ground;
an input applied to a gate of each of said stack of said plurality of field effect transistors (FETs);
said stack of a plurality of field effect transistors (FETS) providing an output at a junction of a predetermined pair of said plurality of field effect transistors (FETs);
a FET floating body of each of said stack of said plurality of field effect transistors (FETs) being connected to a voltage supply rail; and
at least one feedback field effect transistor (FET), said at least one feedback field effect transistor (FET) including a plurality of N-channel field effect transistors (NFETs), said plurality of feedback NFETs connected between a junction of a predefined pair of said plurality of field effect transistors (FETs) and said output; and
each of said plurality of feedback NFETs having a gate coupled to a respective junction of a respective pair of said plurality of field effect transistors (FETs) and having a source coupled to respective next junction of a respective next successive pair of said plurality of field effect transistors (FETs);
said plurality of feedback NFETs for threshold adjustment of a V+ switching trip point of the SOI CMOS Schmitt trigger circuit.
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14. A method for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications, the SOI CMOS Schmitt trigger circuit including a stack of a plurality of P-channel and N-channel field effect transistors (PFETs and NFETs) connected in series between a voltage supply and ground, each receiving a gate input and providing an output between a predetermined pair of the FETs;
- and at least one feedback FET having a source coupled a junction of a predefined pair of the plurality of field effect transistors (FETs) and having a gate coupled to the output, said method comprising the steps of;
connecting a FET floating body of each of the PFETS in the stack to a positive voltage supply rail; and
connecting a FET floating body of each of the NFETS in the stack to a voltage supply ground rail. - View Dependent Claims (15, 16, 17, 18)
- and at least one feedback FET having a source coupled a junction of a predefined pair of the plurality of field effect transistors (FETs) and having a gate coupled to the output, said method comprising the steps of;
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19. A method for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications, the SOI CMOS Schmitt trigger circuit including a stack of a plurality of P-channel and N-channel field effect transistors (PFETs and NFETs) connected in series between a voltage supply and ground, each receiving a gate input and providing an output between a predetermined pair of the FETs;
- and at least one feedback FET having a source coupled a junction of a predefined pair of the plurality of field effect transistors (FETs) and having a gate coupled to the output, and wherein the at least one feedback FET comprises a plurality of feedback P-channel field effect transistors (PFETs), said method comprising the steps of;
connecting a FET body of each of the PFETS in the stack to a positive voltage supply rail;
connecting a FET body of each of the NFETS in the stack to a voltage supply ground rail;
connecting said plurality of feedback PFETs between said junction of said predefined pair of the plurality of field effect transistors (FETs) and said output; and
connecting a source of each of said plurality of feedback PFETs to a respective junction of a respective pair of said plurality of field effect transistors (FETs) and connecting a gate of each of said plurality of feedback PFETs to a respective next junction of a respective next successive pair of said plurality of field effect transistors (FETs);
said plurality of feedback PFETs for threshold adjustment of the V−
switching trip point of the SOI CMOS Schmitt trigger circuit.
- and at least one feedback FET having a source coupled a junction of a predefined pair of the plurality of field effect transistors (FETs) and having a gate coupled to the output, and wherein the at least one feedback FET comprises a plurality of feedback P-channel field effect transistors (PFETs), said method comprising the steps of;
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20. A method for adapting a CMOS Schmitt trigger circuit for deep sub-micrometer partially depleted SOI (PD/SOI) applications, the SOI CMOS Schmitt trigger circuit including a stack of a plurality of P-channel and N-channel field effect transistors (PFETs and NFETs) connected in series between a voltage supply and ground, each receiving a gate input and providing an output between a predetermined pair of the FETs;
- and at least one feedback FET having a source coupled a junction of a predefined pair of the plurality of field effect transistors (FETs) and having a gate coupled to the output, and wherein the at least one feedback FET comprises a plurality of feedback N-channel field effect transistors (NFETs), said method comprising the steps of;
connecting a FET body of each of the PFETS in the stack to a positive voltage supply rail;
connecting a FET body of each of the NFETS in the stack to a voltage supply ground rail;
connecting said plurality of feedback NFETs between said junction of said predefined pair of the plurality of field effect transistors (FETs) and said output; and
connecting a gate of each of said plurality of feedback NFETs to a respective junction of a respective pair of said plurality of field effect transistors (FETs) and connecting a source of each of said plurality of feedback PFETs to a respective next junction of a respective next successive pair of said plurality of field effect transistors (FETs);
said plurality of feedback NFETs for threshold adjustment of the V+ switching trip point of the SOI CMOS Schmitt trigger circuit.
- and at least one feedback FET having a source coupled a junction of a predefined pair of the plurality of field effect transistors (FETs) and having a gate coupled to the output, and wherein the at least one feedback FET comprises a plurality of feedback N-channel field effect transistors (NFETs), said method comprising the steps of;
Specification