Analog to digital converter with enhanced differential non-linearity

• US 6,441,765 B1
• Filed: 08/22/2000
• Issued: 08/27/2002
• Est. Priority Date: 08/22/2000
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Aram, Farbod
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US09/643,819
• Time in Patent Office: 735 Days
• Field of Search: 341/155, 341/144, 341/161, 327/541
• US Class Current: 341/155
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

A bit-and-one-half analog to digital converter comprising a multiplying analog to digital converter (MDAC) operating in cooperation with a comparator which generates a two-bit digital output signal by comparison of an output of the MDAC against a pair of thresholds, wherein the thresholds are stretched outwardly from symmetrical thresholds centered at +/−¼ of the comparison range.

Claims

1. A bit-and-one-half analog to digital converter comprising a multiplying analog to digital converter operating in cooperation with a comparator which generates a digital output signal by comparison of an output of said multiplying analog to digital converter against a pair of thresholds, wherein said thresholds are stretched outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.

2. A bit-and-one-half analog to digital converter according to claim 1, wherein each of the thresholds is stretched outwardly by ⅛

of the comparison range.

3. A bit-and-one-half analog to digital converter according to claim 1, wherein said comparator generates a two-bit digital output.

4. A bit-and-one-half analog to digital converter comprising:

a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage; and

a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;

wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output; and

wherein said comparator generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.

5. A bit-and-one-half analog to digital converter according to claim 4, wherein said thresholds are each stretched outwardly by ⅛

of the comparison range.

6. A bit-and-and-one-half analog to digital converter according to claim 4, further comprising a resistor ladder for generating the thresholds.

7. A bit-and-one-half analog to digital converter according to claim 6, wherein said resistive ladder generates a first threshold spaced ¼

of the comparison range from a most negative comparison voltage, and a second threshold spaced ¼

of the comparison range from a most positive comparison voltage.

8. A bit-and-one-half analog to digital converter according to claim 6, wherein said comparator generates a two-bit digital output.

9. A multi-stage pipelined analog to digital converter comprising:

plural stages arranged in series relative to each other, each stage accepting an input analog voltage and generating a residual analog voltage together with a digital output; and

a correction circuit for accepting the digital output from each of said plural stages and for generating a digital output in correspondence to an analog input voltage;

wherein each stage comprises a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage and a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;

wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output; and

wherein said comparator generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.

10. A multi-stage pipelined analog to digital converter according to claim 9, wherein said thresholds are each stretched outwardly by ⅛

of the comparison range.

11. A multi-stage pipelined analog to digital converter according to claim 9, further comprising a resistor ladder for generating the thresholds.

12. A multi-stage pipelined analog to digital converter according to claim 11, wherein said resistive ladder generates a first threshold spaced ¼

of the comparison range from a most negative comparison voltage, and a second threshold spaced ¼

of the comparison range from a most positive comparison voltage.

13. A multi-stage pipelined analog to digital converter according to claim 9, wherein said comparator generates a two-bit digital output.

14. A bit-and-one-half analog to digital converter comprising multiplying analog to digital converter (multiplying analog to digital converter ) means for operating in cooperation with comparator means for generating a digital output signal by comparison of an output of said multiplying analog to digital converter means against a pair of thresholds, wherein said thresholds are stretched outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.

15. A bit-and-one-half analog to digital converter according to claim 14, wherein each of the thresholds is stretched outwardly by ⅛

of the comparison range.

16. A bit-and-one-half analog to digital converter according to claim 14, wherein said comparator means generates a two-bit digital output.

17. A bit-and-one-half analog to digital converter comprising:

switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage; and

comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;

wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator means and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output; and

wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.

18. A bit-and-one-half analog to digital converter according to claim 17, wherein said thresholds are each stretched outwardly by ⅛

of the comparison range.

19. A bit-and-one-half analog to digital converter according to claim 17, further comprising resistor ladder means for generating the thresholds.

20. A bit-and-one-half analog to digital converter according to claim 19, wherein said resistive ladder means generates a first threshold spaced ¼

of the comparison range from a most negative comparison voltage, and a second threshold spaced ¼

of the comparison range from a most positive comparison voltage.

21. A bit-and-one-half analog to digital converter according to claim 19, wherein said comparator means generates a two-bit digital output.

22. A multi-stage pipelined analog to digital converter comprising;

plural stage means arranged in series relative to each other, each stage means for accepting an input analog voltage and for generating a residual analog voltage together with a digital output; and

correction circuit means for accepting the digital output from each of said plural stage means and for generating a digital output in correspondence to an analog input voltage;

wherein each stage means comprises a switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage and a comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;

wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a pair of switched capacitors, and generates the amplified analog output voltage during a second amplification phase in which one of the capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator means and in which the other capacitor is biased with a reference voltage also selected in dependence on the digital output; and

wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a pair of thresholds, said thresholds being stretched outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.

23. A multi-stage pipelined analog to digital converter according to claim 22, wherein said thresholds are each stretched outwardly by ⅛

of the comparison range.

24. A multi-stage pipelined analog to digital converter according to claim 22, further comprising resistor ladder means for generating the thresholds.

25. A multi-stage pipelined analog to digital converter according to claim 24, wherein said resistive ladder means generates a first threshold spaced ¼

of the comparison range from a most negative comparison voltage, and a second threshold spaced ¼

of the comparison range from a most positive comparison voltage.

26. A multi-stage pipelined analog to digital converter according to claim 22, wherein said comparator means generates a two-bit digital output.

27. A bit-and-one-half analog to digital converter comprising:

a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage; and

a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;

wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator and in which at least another one of the capacitors is biased with a reference voltage; and

wherein said comparator generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds.

28. A bit-and-one-half analog to digital converter according to claim 27, wherein the reference voltage also selected in dependence on the digital output.

29. A bit-and-one-half analog to digital converter according to claim 27, wherein said plurality of thresholds are stretched outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.

30. A multi-stage pipelined analog to digital converter comprising:

plural stages arranged in series relative to each other, each stage accepting an input analog voltage and generating a residual analog voltage together with a digital output; and

a correction circuit for accepting the digital output from each of said plural stages and for generating a digital output in correspondence to an analog input voltage;

wherein each stage comprises a switched capacitive sample and amplification circuit that accepts an analog input voltage and generates a multiplied analog output voltage and a comparator which generates a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit;

wherein said switched capacitive sample and amplification circuit samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator and in which at least another one of the capacitors is biased with a reference voltage; and

wherein said comparator generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds.

31. A multi-stage pipelined analog to digital converter according to claim 30, wherein the reference voltage also selected in dependence on the digital output.

32. A multi-stage pipelined analog to digital converter according to claim 30, wherein said plurality of thresholds are stretched outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.

33. A bit-and-one-half analog to digital converter comprising:

switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage; and

comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;

wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator means and in which at least another one of the capacitors is biased with a reference voltage; and

wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds.

34. A bit-and-one-half analog to digital converter according to claim 33, wherein the reference voltage also selected in dependence on the digital output.

35. A bit-and-one-half analog to digital converter according to claim 33, wherein said plurality of thresholds are stretched outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.

36. A multi-stage pipelined analog to digital converter comprising:

plural stage means arranged in series relative to each other, each stage means for accepting an input analog voltage and for generating a residual analog voltage together with a digital output; and

correction circuit means for accepting the digital output from each of said plural stage means and for generating a digital output in correspondence to an analog input voltage;

wherein each stage means comprises a switched capacitive sample and amplification circuit means for accepting an analog input voltage and for generating a multiplied analog output voltage and a comparator means for generating a digital output based on the analog output voltage generated by said switched capacitive sample and amplification circuit means;

wherein said switched capacitive sample and amplification circuit means samples the analog input voltage during a first sampling phase in which the voltage is stored on a plurality of capacitors, and generates the amplified analog output voltage during a second amplification phase in which at least one of the plurality of capacitors is switched into a feedback amplification circuit in dependence on the digital output from said comparator means and in which at least another one of said capacitors is biased with a reference voltage; and

wherein said comparator means generates the digital output by comparison of the generated analog output voltage against a plurality of thresholds.

37. A multi-stage pipelined analog to digital converter according to claim 36, wherein the reference voltage also selected in dependence on the digital output.

38. A multi-stage pipelined analog to digital converter according to claim 36, wherein said plurality of thresholds are stretched outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.

39. A method of converting an analog signal into a digital signal, comprising the steps of:

(a) sampling an analog input during a sampling phase;

(b) storing the analog input in a plurality of capacitors;

(c) generating an amplified analog output voltage during an amplifying phase;

(d) comparing the amplified analog output voltage with a plurality of threshold voltages;

(e) switching at least one of the plurality of capacitors into a feedback arrangement in accordance with step (d); and

(f) biasing at least another one of the plurality of capacitors with a reference voltage.

40. A method according to claim 39, wherein step (f) comprises selecting the reference voltage in accordance with step (d).

41. A method according to claim 39, wherein step (d) comprises the step of stretching the plurality of thresholds outwardly from symmetrical thresholds centered at +/−

¼

of the comparison range.