Flash memory with multiple status reading capability

• US 6,442,076 B1
• Filed: 06/30/2000
• Issued: 08/27/2002
• Est. Priority Date: 06/30/2000
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/609,037
• Time in Patent Office: 788 Days
• Field of Search: 365/195, 365/185.33, 365/230.03, 365/233, 365/189.04, 365/189.03
• US Class Current: 365/185.33
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The memory automatically provides status data when a read command is received for a memory array location that is currently subject to a write operation. The automatic status output allows multiple processors to access the memory device without substantial bus master overhead. The memory can also output status data in response to a status read command.

Claims

1. A method of operating a memory device comprising:

initiating a write operation on a first block of an array of memory cells;

initiating a first read operation on the first block during the write operation; and

automatically outputting a write status in response to initiating the first read operation, wherein the write status indicates that the write operation is being performed on the first block.

2. The method of claim 1 further comprises:

setting a bank register in response to initiating the write operation; and

comparing a read address to the bank register prior to outputting the write status.

3. The method of claim 1 wherein the memory device is a synchronous non-volatile memory device.

4. The method of claim 1 wherein the memory device comprises four memory array banks.

5. The method of claim 1 wherein initiating the write operation comprises setting a bank register to identify that the write operation is being performed on the first bank.

6. A method of operating a memory device comprising:

initiating a write operation on a first block of an array of memory cells, wherein initiating the write operation comprises setting a bank register to identify that the write operation is being preformed on the first bank;

initiating a first read operation on the first block during the write operation;

automatically outputting a write status in response to initiating the first read operation, wherein the write status indicates that the write operation is being performed on the first block;

initiating a second read operation on a second block during the write operation on the first bank;

comparing a read address of the second block to the bank register; and

outputting data read from the second block while the write operation is being executed.

7. A method of controlling a memory device comprising:

executing a write operation on a first addressable block of an array of memory cells;

setting a bank register to a first state while the write operation is being performed, wherein the first state indicates that the first block is being written to;

initiating a first read operation in response to a read command received during execution of the write operation;

comparing a read address provided with the read command to the bank register; and

automatically outputting a write status in response to the read command if the read address is located in the first block, wherein the write status indicates that the write operation is being performed on the first block.

8. The method of claim 7 wherein the write operation is executed in response to a write command provided by a first external processor.

9. The method of claim 8 wherein the read command is provided by a second external processor.

10. The method of claim 7 wherein the memory device is a synchronous non-volatile memory device having four memory array banks.

11. The method of claim 10 wherein the bank register is a four-bit register corresponding to the four memory array banks.

12. A method of controlling a memory device comprising:

coupling a write command, a write address and write data from a first processor to the memory device;

executing a write operation on a first addressable block of an array of memory cells, wherein the first addressable block corresponds to the write address;

setting a bank register to a first state while the write operation is being executed, wherein the first state indicates that the first block is being written to;

coupling a read command and a read address from a second processor to the memory device;

initiating a first read operation in response to a read command received during execution of the write operation;

comparing the read address provided with the read command to the bank register; and

automatically outputting a write status in response to the read command if the read address corresponds to the first block, wherein the write status indicates that the write operation is being executed on the first block.

13. The method of claim 12 wherein the memory device is a synchronous non-volatile memory device having four memory array banks and the bank register is a four-bit register corresponding to the four memory array banks.

14. The method of claim 13 further comprises:

using the second processor, requesting a memory write status of the memory device; and

outputting memory write status data in response to the memory write status request, wherein the memory write status data indicates any location within the memory subject to a data write operation.